ICS650-14B Integrated Circuit System, ICS650-14B Datasheet - Page 3

• Manufacturer Part Number: ICS650-14B
• Description: Networkingclock Source
• Manufacturer: Integrated Circuit System

MDS 650-14B B
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone]te l • www.icst.com
External Components
Electrical Specifications
The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling capacitors
of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and 14, as close to the
ICS650R-14B as possible. A series termination resistor of 33
crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground
to optimize the initial accuracy. The value of these capacitors is given by the following equation, where C L is the
crystal load capacitance: Crystal caps (pF) = (C L -6) x 2. For a crystal with 16 pF load capacitance, two 20 pF caps
should be used.
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V unless noted)
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH, SEL pins only
Input Low Voltage, VIL, SEL pins only
Input High Voltage, VIH, OE pin only
Input Low Voltage, VIL, OE pin only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
AC CHARACTERISTICS (VDD = 3.3V unless noted)
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Frequency error
Absolute Jitter, short term
2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.
affect device reliability.
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
Conditions
Referenced to GND
Referenced to GND
Industrial "I" version
Max of 20 seconds
Clock Input
Clock Input
IOH=-12mA
IOL=12mA
IOH=-8mA
No Load, VDD = 3.3V
Each output
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
All clocks
CLKB = 27M
CLKC = 6.25M
Other Clocks
3
may be used for each clock output. The 25.00 MHz
Minimum
Networking System Clock
VDD/2 + 1
VDD - 0.5
VDD-0.4
-0.5
-40
-65
2.0
2.4
45
0
3
Typical
25.000
±250
±150
±50
32
50
Maximum
VDD/2 - 1
VDD+0.5
ICS650-14B
260
150
5.5
0.5
0.8
0.4
1.5
1.5
70
85
55
7
0
Revision 072401
Units
MHz
ppm
mA
mA
ns
ns
ps
ps
ps
°C
°C
°C
°C
%
V
V
V
V
V
V
V
V
V
V
V
V