pt7a4409 Pericom Technology Inc, pt7a4409 Datasheet - Page 14

• Manufacturer Part Number: pt7a4409
• Description: T1/e1/oc3 System Synchronizer
• Manufacturer: Pericom Technology Inc

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Applications Information
Master Clock
The PT7A4409/4409L uses either an external clock source or an
external crystal as the master timing source.
In Free-Run State, the frequency tolerance of the PT7A4409/
4409L output clocks are equal to the frequency tolerance of the
timing source. In an application, if an accurate Free-Run State is
not required, the tolerance of the master timing source may be
100ppm. If required, the tolerance must be no greater than 32ppm.
The capture range of PT7A4409/4409L will also be considered
when deciding the accuracy of the master timing source. The
sum of the accuracy of the master timing source and the cap-
ture range of the PT7A4409/4409L will always equal 230ppm.
For example, if the master timing source is 100ppm, the capture
range will be 130ppm.
• Clock Oscillator
If using an external clock source, its output pin should be con-
nected directly (not AC coupled) to the OSCi pin of the
PT7A4409/4409L and the OSCo pin of PT7A4409/4409L can be
left open as shown in Figure 9 or connected as an output pin.
When selecting the clock oscillator, following specifications
should be considered. They are
Refer to AC Electrical Characteristics.
PT0103(12/05)
Figure 9. Clock Oscillator Connection
- absolute frequency
- frequency change over temperature
- output rise and fall time
- duty cycle
output level
PT7A4409/4409L
OSCo
No Connection
OSCi
20MHz OUT
+5V
GND
+5V
0.1µF
14
• Crystal Oscillator
If a crystal oscillator is selected as the master timing source, it
should be connected to the PT7A4409/4409L as shown in Fig-
ure 10.
Guard Time Adjustment Circuit
AT&T TR62411 recommends that excessive switching of the
timing reference should be minimized. Switching between refer-
ences should be performed only when the primary signal is
degraded.
The Holdover State is used to minimize reference source switch-
ing (from PRI to SEC). When the PRI signal is degraded, the
PT7A4409/4409L enters Holdover State for a predetermined maxi-
mum time (i.e., guard time). If the PRI signal returns to normal
before the expiration of the guard time (level at GTi pin is low),
the PT7A4409/4409L will return to Normal State with PRI input
reference. If the PRI signal is still degraded after expiration of
the guard time (level at GTi becomes high), the reference switch-
ing (from PRI to SEC) will occur.
Figure 10. Crystal Oscillator Connection
he crystal specification is as follows:
PT7A4409/4409L
- Frequency:
- Tolerance:
- Oscillation Mode:
- Resonance Mode:
- Load Capacitance:
- Maximum Series Resistance:
- Approximate Drive Level:
T1/E1/OC3 System Synchronizer
OSCo
OSCi
1MΩ
56pF
100Ω
20MHz
PT7A4409/4409L
Fundamental
20MHz
as required
Parallel
32pF
35Ω
1mW
39pF
Data Sheet
3-50pF
Ver:2