pt7a4409 Pericom Technology Inc, pt7a4409 Datasheet - Page 16

• Manufacturer Part Number: pt7a4409
• Description: T1/e1/oc3 System Synchronizer
• Manufacturer: Pericom Technology Inc

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
Reset Circuit
A simple power up reset circuit with about a 50µs reset active
(low) time is shown in Figure 14. Resistor R
only. The reset low time is not critical but should be greater
than 300ns.
Power Supply Decoupling
The PT7A4409/4409L has two V
Power decoupling capacitors should be included as shown in
Figure 15.
PT0103(12/05)
Figure 14. Power-up Reset Circuit
Figure 15. Power Supply Decoupling
PT7A4409/4409L
0.1µF
C2
31
28
+
RST
PT7A4409
/4409L
1
1kΩ
17
10
R
7
P
CC
0.1µF
C1
+
+
10kΩ
pins and two GND pins.
R
+5V
0.1µF
P
C3
is for protection
10nF
C
16
Detailed Specifications
Definitions of Critical Performance Specifictions
Intrinsic Jitter: Intrinsic jitter is the jitter produced by the
synchronizing circuit. It is measured by applying a reference
signal with no jitter to the input of the device, and measuring its
output jitter. Intrinsic jitter may also be measured when the
device is in a non-synchronizing mode - such as free running
or holdover - by measuring the output jitter of the device. In-
trinsic jitter is usually measured with various band limiting fil-
ters depending on the applicable standards.
Jitter Tolerance: Jitter tolerance is a measure of the ability of a
PLL to operate properly (i.e., remain in lock and/or regain lock in
the presence of large jitter magnitudes at various jitter frequen-
cies) when jitter is present on its reference. The applicable stan-
dard specifies how much jitter to apply to the reference when
testing for jitter tolerance.
Jitter Transfer: Jitter transfer or jitter attenuation refers to the
magnitude of jitter at the output of a device with respect to a
given amount of jitter at the input of the device. Input jitter is
applied at various amplitudes and frequencies, and output jitter
is measured with various filters depending on the applicable
standards.
Its 3 possible input frequencies and 9 outputs give the
PT7A4409/4409L 27 possible jitter transfer combinations. How-
ever, only three cases of the jitter transfer specifications are
given in the AC Electrical Characteristics; as the remaining com-
binations can be derived from them.
For the PT7A4409/4409L, two internal elements determine the
jitter attenuation. They are internal 1.9Hz low pass loop filter
and phase slope limiter. The phase slope limiter limits the out-
put phase slope to 5ns/125µs. Therefore, if the input signal
exceeds this rate, such as for very large amplitude low frequency
input jitter, the maximum output phase slope will be limited (i.e.,
attenuated) to 5ns/125µs.
It should be noted that 1UI at 1.544MHz (644ns) is not equal to
1UI at 2.048MHz (488ns). A transfer value using different input
and output frequencies must be calculated in common units
(e.g., seconds) as shown in the following example.
Example : When the T1 input jitter is 20UI (T1 UI Units) and the
T1 to T1 jitter attenuation is 18dB, The T1 and E1 output jitter
can be calculated as follows:
T1/E1/OC3 System Synchronizer
PT7A4409/4409L
Data Sheet
Ver:2