mm912f634 Freescale Semiconductor, Inc, mm912f634 Datasheet - Page 240

• Manufacturer Part Number: mm912f634
• Description: Mm912f634 - Integrated S12 Based Relay Driver With Lin
• Manufacturer: Freescale Semiconductor, Inc

Functional Description and Application Information
4.32
4.32.1
This specification describes the function of the Clocks and Reset Generator (S12SCRGV1).
4.32.1.1
The main features of this block are:
4.32.1.2
This subsection lists and briefly describes all operating modes supported by the 9S12I32PIMV1.
4.32.1.2.1
Freescale Semiconductor
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Internal 32 kHz reference clock generator:
— Trimmable in frequency
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— Factory trimmed value in Flash Memory
Optional external crystal or resonator:
— Full swing Pierce Oscillator for crystals or resonators from 4.0 MHz to 16 MHz
— Oscillator Monitor to detect loss of clock
Internal digitally controlled oscillator (DCO):
— Allows to generate frequencies in the range from 32 MHz to 40 MHz
— Stable frequency by using a reference clock in a Frequency Locked Loop (FLL).
— FLL based on either Internal Reference Clock (32 kHz) or optional external crystal/resonator (for higher accuracy).
— Interrupt request on entry or exit from FLL locked condition
Bus Clock Generator
— Clock switch for DCO or optional external crystal/resonator based Bus Clock
— Bus Clock divider to choose system speed
System Reset generation from the following possible sources:
— Power-on detect
— Illegal address access
— COP timeout
— Loss of external Oscillator Clock (Oscillator monitor fail)
— External pin RESET
FLL Engaged Internal (FEI)
— This is the default mode after System Reset and Power-on Reset.
— The FLL reference is the Internal Reference Clock.
— The Bus Clock is based on the DCO Clock.
FLL Engaged External (FEE)
— This mode is entered by:
— The FLL reference is the Oscillator Clock.
— The Bus Clock is based on the DCO Clock.
FLL Bypassed External (FBE)
— This mode is entered by:
— The DCO Clock is turned off.
— The Bus Clock is based on the Oscillator Clock.
S12S Clocks and Reset Generator (S12SCRGV1)
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– enabling the external Oscillator (OSCEN bit)
– programming the reference divider (RDIV[2:0] bits)
– selecting the divided down Oscillator Clock as FLL reference clock (REFS bit)
– enabling the external Oscillator (OSCEN bit)
– selecting the Oscillator Clock as basis for Bus Clock (BCLKS bit)
Introduction
2% deviation over voltage and temperature for a fixed trim value.
Features
Modes of Operation
Run Mode
S12S Clocks and Reset Generator (S12SCRGV1)
MM912F634
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