wm8982gefl-v Wolfson Microelectronics plc, wm8982gefl-v Datasheet - Page 67

• Manufacturer Part Number: wm8982gefl-v
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
AUDIO SAMPLE RATES
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
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The WM8982 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs
for the digital filters and the ALC attack/decay times stated are determined using these values and
assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the closest
SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay
and hold times will scale appropriately.
Table 53 Sample Rate Control
The WM8982 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8982 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1 and/or GPI04) a clock for another part of the system that is
derived from an existing audio master clock.
Figure 45 shows the PLL and internal clocking arrangment on the WM8982.
The PLL can be enabled or disabled by the PLLEN register bit.
Table 54 PLLEN Control Bit
R7
Additional
Control
R1
Power
management 1
REGISTER
ADDRESS
REGISTER
ADDRESS
3:1
BIT
5
BIT
SR
LABEL
PLLEN
LABEL
000
0
DEFAULT
DEFAULT
PLL enable
0=PLL off
1=PLL on
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
DESCRIPTION
PP, Rev 3.2, September 2008
DESCRIPTION
WM8982
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