wm8982gefl-v Wolfson Microelectronics plc, wm8982gefl-v Datasheet - Page 77

• Manufacturer Part Number: wm8982gefl-v
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
Figure 50 ADC Power Up and Down Sequence (not to scale)
w
BIASEN bits
Power Supply
POR
I
ADC Internal
Analogue Inputs
ADCDAT pin
ADCEN bit
(Note 3)
INPPGAEN bit
2
VMIDSEL/
S Clocks
State
(Note 4)
V
pora
POR Undefined
No Power
V
por_on
Power down
AVDD/2
DGND
Notes:
This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs.
This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and
outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x (AVDD/2) (using output 1.5x
boost) in a way that is controlled and predictable (see note 2).
Choose the value of the VMIDSEL bits based on the startup time (VMIDSEL=10 for slowest startup,
VMIDSEL=11 for fastest startup). Startup time is defined by the value of the VMIDSEL bits (the
reference impedance) and the external decoupling capacitor on VMID.
Setting DACEN to off while operating in x1.5 boost mode will cause the VMID voltage to drop to
AVDD/2 midrail level and cause an output pop.
In addition to the power on sequence, it is recommended that the zero cross functions are used when
changing the volume in the PGAs to avoid any audible pops or clicks.
Table 62 Typical POR Operation (simulated values)
ADC Group Delay
(Note 1)
SYMBOL
t
t
POR
midrail_on
midrail_off
t
adcint
t
midrail_on
DNC
Init
t
adcint
GD
MIN
Normal Operation
ADC enabled
TYPICAL
29/fs
500
>10
2/fs
GD
INPPGA enabled
Device Ready
VMID enabled
ADC off
DNC
PD
MAX
Init
GD
t
adcint
UNIT
n/fs
n/fs
ms
s
ADC enabled
Normal Operation
GD
PP, Rev 3.2, September 2008
t
midrail_off
Internal POR active
Power down
(Note 2)
V
por_off
WM8982
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