wm8941 Wolfson Microelectronics plc, wm8941 Datasheet - Page 31

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wm8941

Manufacturer Part Number
wm8941
Description
Mono Codec With Speaker Driver And Video Buffer
Manufacturer
Wolfson Microelectronics plc
Datasheet

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Figure 12 ALC Normal Mode Operation
Table 20 ALC Control Registers
NORMAL MODE
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
If there is no analogue input signal present when the ALC is enabled, the ALC may not function
correctly. To ensure correct operation of the ALC with no analogue input signal, the Input PGA
Volume control register (R45) should be written with the INPPGAMUTE and ALCZC bits set to 0
before setting the ALCSEL bit to 1 in register R32 (bit 8).
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing
the gain of the PGA. The following diagram shows an example of this.
R42 (2Ah)
ALC Control 4
REGISTER
ADDRESS
1
BIT
ALCZC
LABEL
0 (zero cross
off)
DEFAULT
ALC uses zero cross detection circuit.
0 = Disabled (recommended)
1 = Enabled
DESCRIPTION
PD, Rev 4.0, August 2008
WM8941
31

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