wm8782a Wolfson Microelectronics plc, wm8782a Datasheet - Page 9

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wm8782a

Manufacturer Part Number
wm8782a
Description
24-bit, 192khz Stereo Adc
Manufacturer
Wolfson Microelectronics plc
Datasheet

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AUDIO INTERFACE TIMING – SLAVE MODE
Table 2 Digital Audio Data Timing – Slave Mode
Note:
LRCLK should be synchronous with MCLK, although the WM8782A interface is tolerant of phase variations or jitter on
these signals.
Test Conditions
DVDD = 3.3V, DGND = 0V, T
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
Figure 2 Digital Audio Data Timing – Slave Mode
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
SYMBOL
t
t
t
t
LRSU
t
BCH
t
BCY
BCL
LRH
DD
50
20
20
10
10
MIN
0
TYP
PD, April 2010, Rev 4.8
MAX
10
WM8782A
UNIT
ns
ns
ns
ns
ns
ns
9

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