wm8775 Wolfson Microelectronics plc, wm8775 Datasheet - Page 23

• Manufacturer Part Number: wm8775
• Description: 24-bit, 96khz Adc With 4 Channel I/p Multiplexer
• Manufacturer: Wolfson Microelectronics plc

Production Data
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MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8775 generates ADCLRC and BCLK. These clocks are derived from the
master clock. The ratio of MCLK to ADCLRC is set by ADCRATE.
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the
ADC signal processing oversample rate to 64fs.
POWERDOWN MODE AND ADC DISABLE
Setting the PDWN register bit immediately powers down the WM8775, including the references,
overriding all other powerdown control bits. All trace of the previous input samples is removed, but all
control register settings are preserved. When PDWN is cleared, the digital filters will be re-initialised.
It is recommended that the 4-channel input mux and buffer, and ADC are powered down before
setting PDWN.
The ADC may also be powered down by setting the ADCPD disable bit. Setting ADCPD will disable
the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when
ADCPD is reset.
ADC Oversampling Rate
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
ADCLRC Frequency
Powerdown Control
R12(0Ch)
R12(0Ch)
R13(0Dh)
0001100
0001100
0001101
Select
BIT
2:0
BIT
BIT
3
0
1
6
ADCRATE[2:0]
ADCOSR
ADCPD
LABEL
PDWN
AINPD
LABEL
LABEL
DEFAULT
DEFAULT
0
0
0
DEFAULT
0
010
Power Down Mode Select:
ADC Disable:
Analogue Input Disable:
ADC oversampling rate select
0 : Normal Mode
1: Power Down Mode
0 : Normal Mode
1: Power Down Mode
0 : Normal Mode
1 : Power Down Mode
Master Mode MCLK:ADCLRC
ratio select:
0: 128x oversampling
1: 64x oversampling
010: 256fs
011: 384fs
100: 512fs
101: 768fs
DESCRIPTION
DESCRIPTION
PD, Rev 4.4, October 2008
DESCRIPTION
WM8775
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