wm8595 Wolfson Microelectronics plc, wm8595 Datasheet - Page 26

• Manufacturer Part Number: wm8595
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

WM8595
DIGITAL AUDIO INTERFACE
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Digital audio data is transferred to and from the WM8595 via the digital audio interface. The DACs
have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate
in both master or slave mode The ADC has independent master clock, bit clock and left/right frame
clock in addition to its data output, and can operate in both master and slave modes.
MASTER MODE
The ADC audio interface requires both a left/right frame clock (ADCLRCLK) and a bit clock
(ADCBCLK). These can be supplied externally (slave mode) or they can be generated internally
(master mode). Selection of master and slave mode is achieved by setting ADC_MSTR in ADC
Control Register 3.
The frequency of ADCLRCLK in master mode is dependent upon the ADC master clock frequency
and the ADC_SR[2:0] bits.
The frequency of ADCBCLK in master mode can be selected by ADC_BCLKDIV[1:0].
Both DAC1 and DAC2 operate in slave mode only.
Table 12 ADC Master Mode Control
ADC_CTRL2
ADC_CTRL3
REGISTER
ADDRESS
R14
0Eh
R15
0Fh
BIT
2:0
5:3
0
ADC_BCLK
DIV[2:0]
SR[2:0]
LABEL
MSTR
ADC_
ADC_
DEFAULT
000
000
0
ADC MCLK:LRCLK Ratio
000 = Auto detect
001 = 128fs
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = Reserved
ADC BCLK Rate
000 = MCLK / 4
001 = MCLK / 8
010 = 32fs
011 = 64fs
100 = 128fs
All other values of ADC_BCLKDIV[2:0] are
reserved
ADC Master Mode Select
0 = Slave mode, ADCBCLK and ADCLRCLK
are inputs to WM8595
1 = Master mode, ADCBCLK and
ADCLRCLK are outputs from WM8595
DESCRIPTION
PD, Rev 4.1, April 2010
Production Data
26