wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 52

• Manufacturer Part Number: wm8593seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

WM8593
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ADC AUDIO INTERFACE CLOCK CONFIGURATION
The WM8593 ADC has an independent audio interface which can be configured to select the
required signals from any of the digital audio ports. The audio interface is not restricted to take each
signal from the same digital audio port, although the BCLK and LRCLK signals are selected together.
For example, it is possible to use MCLK1, BCLK2, LRCLK2 and DIO5 as the digital audio port pins
that connect to the ADC audio interface through the audio interface mux if required.
The MCLK is always an input to the ADC audio interface is selected using ADCMCLK_SEL[2:0]. The
BCLK and LRCLK are always selected together, and can be either an input to the ADC audio
interface (when the ADC is in slave mode) or an output from the ADC audio interface (when the ADC
is in master mode). BCLK and LRCLK are selected using ADCWORDCLK_SEL[2:0].
DAC1 AND DAC2 AUDIO INTERFACE CLOCK CONFIGURATION
Both DACs on the WM8593 have independent audio interfaces which can be configured to select the
required signals from any of the digital audio ports. The audio interfaces are not restricted to take
each signal from the same digital audio ports, although the BCLK and LRCLK signals are selected
together. For example, it is possible to use MCLK1, BCLK2, LRCLK2 and DIO5 as the digital audio
port pins that connect to the DAC1 audio interface through the audio interface mux, while using
MCLK2, BCLK1, LRCLK1 and DIO3 for DAC2 if required.
DAC1MCLK and DAC2MCLK are always inputs to the DAC1 and DAC2 audio interfaces and are
selected using DAC1MCLK_SEL[2:0] and DAC2MCLK_SEL[2:0] respectively.
DAC1BCLK and DAC1LRCLK are always selected together, and can be either an input to the DAC1
audio interface (when DAC1 is in slave mode) or an output from the DAC1 audio interface (when
DAC1 is in master mode). DAC2BCLK and DAC2LRCLK are always selected together, and can be
either an input to the DAC2 audio interface (when DAC2 is in slave mode) or an output from the
DAC2 audio interface (when DAC2 is in master mode). DAC1BCLK and DAC1LRCLK are selected
using DAC1WORDCLK_SEL[2:0], while DAC2BCLK and DAC2LRCLK are selected using
DAC2WORDCLK_SEL[2:0].
Finally, the data input to the DAC1 audio interface is configured using DAC1DIN_SEL[2:0] and the
data input to the DAC2 audio interface is configured using DAC2DIN_SEL[2:0]
Table 38 ADC Audio Interface Clock Configuration
REGISTER
ADDRESS
AIF_MUX8
R44
2Ch
BIT
3:1
6:4
SEL[2:0]
SEL[2:0]
LABEL
MCLK_
WORD
CLK_
ADC
ADC
DEFAULT
000
000
ADCMCLK Select
000 = Use MCLK1
001 = Use MCLK2
010 = Use MCLK3
011 = Use MCLK4
100 = Use MCLK5
101 to 111 = Reserved
ADC BCLK and LRCLK Select
000 = Use BCLK1 and LRCLK1
001 = Use BCLK2 and LRCLK2
010 = Use BCLK3 and LRCLK3
011 = Use BCLK4 and LRCLK4
100 = Use BCLK5 and LRCLK5
101 = Use DAC1BCLK and DAC1LRCLK
(when DAC1 is in master mode)
110 = Use DAC2BCLK and DAC2LRCLK
(when DAC2 is in master mode)
111 = Output ADCBCLK and ADCBCLK
(when ADC is master mode)
DESCRIPTION
PD Rev 4.0 April 2008
Pre-Production
52