wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 86

• Manufacturer Part Number: wm8593seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

WM8593
R37 (25h) – Audio Interface MUX Configuration Register 1 (AIF_MUX1)
Figure 56 R37 – Audio Interface MUX Configuration Register 1
w
Default
Default
WORDCLK1_SEL[2:0]
Write
Write
Read
Read
Bit #
Bit #
MCLK1_SEL[2:0]
PORT1_FORCE
DIO1_SEL[2:0]
PORT1_UPD
Function
SEL[0]
DIO1_
N/A
15
0
7
0
0
Force Port 1 Clocks to Change
0 = Wait until clocks are safe before switching between clock sources
1 = Force clock sources to change immediately
See Table 41 for details of use.
MCLK1 Pin Function Select
000 = Input to WM8593
001 = Output MCLK2
010 = Output MCLK3
011 = Output MCLK4
100 = Output MCLK5
101 to 111 = Reserved
BCLK1 and LRCLK1 Pins Function Select
000 = Inputs to WM8593
001 = Source BCLK2 and LRCLK2
010 = Source BCLK3 and LRCLK3
011 = Source BCLK4 and LRCLK4
100 = Source BCLK5 and LRCLK5
101 = Source DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)
110 = Source DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)
111 = Source ADCBCLK and ADCBCLK (when ADC is master mode)
DIO1 Pin Function Select
000 = Input to WM8593
001 = Source DIO2
010 = Source DIO3
011 = Source DIO4
100 = Source DIO5
101 = Source GPIO1
110 = Source GPIO2
111 = Source ADC Data Output
Port 1 Update
0 = Latch corresponding Port 1 settings into Register Map but do not update
1 = Latch corresponding Port 1 settings into Register Map and update all simultaneously
N/A
14
0
0
6
0
WORDCLK1_SEL[2:0]
N/A
13
0
0
5
0
N/A
12
0
0
4
0
Description
N/A
11
0
3
0
0
N/A = Not Applicable (no function implemented)
MCLK1_SEL[2:0]
PORT1_UPD
10
0
2
0
PD Rev 4.0 April 2008
9
0
1
0
DIO1_SEL[2:1]
Production Data
PORT1_
FORCE
8
0
0
0
86