wm9713 Wolfson Microelectronics plc, wm9713 Datasheet - Page 24

• Manufacturer Part Number: wm9713
• Description: Ac?97 Audio + Touchpanel Codec
• Manufacturer: Wolfson Microelectronics plc

WM9713L
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INTEGER N MODE
The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz which is divided by 4 to achieve
a nominal system clock of 24.576MHz.
The integer division ratio (N) is determined by: F
the range 5 to 12 for integer N operation (0101 = div by 5, 1100 = div by 12). Note that setting LF=1
enables a further division by 4 required for input frequencies in the range 2.048MHz – 4.096MHz.
Integer N mode is selected by setting SDM=0.
FRACTIONAL N MODE
Fractional N mode provides a divide resolution of 1/2
section). The relationship between the required division X, the fractional division K[21:0] and the
integer division N[3:0] is:
where 0 < (X – N) < 1 and K is rounded to the nearest whole number.
For example, if the PLL_IN clock is 13MHz and the desired PLL_OUT clock is 98.304MHz then the
desired division, X, is 7.5618. So N[3:0] will be 7h and K[21:0] will be 23F488h to produce the desired
98.304MHz clock (see Table 5).
Table 5 PLL Modes of Operation
K
2.048MHz
4.096MHz
12.288MHz
13MHz
27MHz (13.5MHz)**
*Divide by 4 enabled in PLL feedback path for low frequency inputs. (LF = 1)
**Divide by 2 enabled at PLL input for frequencies > 14.4MHz > 38MHz (DIVSEL = 1, DIVCTL = 0)
INPUT CLOCK (PLL_IN)
=
2
22
(
X
−
N
)
98.304MHz
98.304MHz
98.304MHz
98.304MHz
98.304MHz
(PLL_OUT)
DESIRED
OUTPUT
PLL
REQUIRED
DIVISION
PLL_out
7.5618
7.2818
(X)
48
24
8
/ F
22
PLL_IN
and is set by K[21:0] (register 46h, see
, and is set by N[3:0] and must be in
FRACTIONAL
DIVISION (K)
0.5618
0.2818
0
0
0
PP Rev 3.2 September 2008
DIVISION (N)
Pre-Production
INTEGER
12x4*
6x4*
8
7
7
24