wm9705seft-v Wolfson Microelectronics plc, wm9705seft-v Datasheet - Page 26

• Manufacturer Part Number: wm9705seft-v
• Description: Multimedia Ac?97 Codec With Integrated Touch Screen Controller
• Manufacturer: Wolfson Microelectronics plc

WM9705
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SLOT 1: COMMAND ADDRESS PORT
The command port is used to control features, and monitor status for the WM9705 functions
including, but not limited to, mixer settings, and power management (refer to the Serial Interface
Register Map). The control interface architecture supports up to 64, 16-bit read/write registers,
addressable on even byte boundaries. Only the even Registers (00h, 02h, etc.) are valid, odd
Register (01h, 03h, etc.) accesses are discouraged (if supported they should default to the
preceding even byte boundary - i.e. a read to 01h will return the 16-bit contents of 00h). The
WM9705’s control register file is nonetheless readable as well as writeable to provide more robust
testability.
Audio output frame slot 1 communicates control register address, and read/write command
information to the WM9705.
COMMAND ADDRESS PORT BIT ASSIGNMENTS
The first bit (MSB) sampled by the WM9705 indicates whether the current control transaction is a
read or write operation. The following 7 bit positions communicate the targeted control register
address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by
the AC’97 controller.
SLOT 2: COMMAND DATA PORT
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle. (As indicated by slot 1, bit 19).
If the current command port operation is a read then the entire time slot must be stuffed with 0s
by the AC’97 controller.
SLOT 3 AND 4: PCM PLAYBACK LEFT AND RIGHT CHANNELS
Audio output frame slots 3 and 4 are the stereo digital audio left and right playback streams. In a
typical Games Compatible PC this data is composed of standard PCM (.wav) output samples
digitally mixed (on the AC’97 controller or host processor) with music synthesis output samples. If
a sample stream of resolution less than 20-bits is transferred, the AC’97 controller must stuff all
trailing non-valid bit positions within this time slot with 0s.
SLOT 5: OPTIONAL MODEM LINE CODEC
This data slot is not supported.
SLOTS 6 AND 9: LFE AND CENTER CHANNEL DATA
Data in these slots may be mapped onto the audio DACs or output as SPDIF/I
control of the mapping bits DSA[1:0] in register 28h and SPSA[1:0] in register 2Ah.
SLOTS 7 AND 8: SURROUND CHANNEL DATA
Data in these slots may be mapped onto the audio DACs or output as SPDIF/I
control of the mapping bits DSA in register 28h and SPSA in register 2Ah.
SLOTS 10 AND 11:
Data in these slots may be mapped onto the audio DACs or output as SPDIF/I
control of the mapping bits DSA in register 28h and SPSA in register 2Ah.
SLOT 12: GPIO
Data in this slot is not supported.
Bit (19)
Bit (18:12)
Bit (11:0)
Bit (19:4)
Bit (3:0)
Read/write command (1 = read, 0 = write)
Control register index (64 16-bit locations, addressed on even
byte boundaries)
Reserved (stuffed with 0s)
Control register write data (stuffed with 0s if current operation is
a read)
Reserved (stuffed with 0s)
PD Rev 4.5 July 2008
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