wm9705seft-v Wolfson Microelectronics plc, wm9705seft-v Datasheet - Page 30

• Manufacturer Part Number: wm9705seft-v
• Description: Multimedia Ac?97 Codec With Integrated Touch Screen Controller
• Manufacturer: Wolfson Microelectronics plc

WM9705
SERIAL INTERFACE REGISTER MAP DESCRIPTION
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Within normal audio frames SYNC is synchronous to the WM9705 input. However, in the absence
of BITCLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to
the WM9705. The WM9705 will not respond with the activation of BITCLK until SYNC has been
sampled low again by the WM9705. This will preclude the false detection of a new audio frame.
PEN DOWN WM9705 WAKE-UP
If pen down is detected when the device is in low power halted mode with PRP[1:0] set to 01 and
RPR set to 1, PR4 will be reset and the CODEC will transition SDATAIN from low to high to
indicate a wakeup to the controller for it to restart the ACLINK. This wakeup mode is disabled
when RPR is set.
POWER DOWN DURING WM9705 RESET – HARDWARE POWER DOWN MODE
Note that the normal default condition of WM9705 when RESETB is applied is ‘all active’.
However, if pin 43 MASK is pulled ‘hi’ during RESETB active, all PR bits are overridden and the
device enters a low power mode. This allows a low power standby mode to be entered without
writing to the device, a condition that is desirable for example, if batteries are changed in a PDA.
The state of MASK is latched on the rising edge of RESETB and if MASK is ‘hi’ the device will
remain in low power mode until register 26h is written to.
(See Table 23)
The serial interface bits perform control functions described as follows: The register map is fully
specified by the AC’97 specification, and this description is simply repeated below, with optional
unsupported features omitted.
RESET REGISTER (INDEX 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to
their default values. Reading this register returns the ID code of the part, indication of modem
support (not supported by the WM9705) and a code for the type of 3D stereo enhancement.
The ID decodes the capabilities of the WM9705 based on the following:
Table 7 Reset Register Function
Note that the WM9705 defaults to indicate 18-bit compatibility.
PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)
These registers manage the output signal volumes. Register 02h controls the stereo master
volume (both right and left channels), Register 04h controls the stereo headphone out, and
Register 06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the
register is the mute bit. When this bit is set to 1 the level for that channel is set at -
ML4 to ML0 is for left channel level, MR4 to MR0 is for the right channel and MM4 to MM0 is for
the mono out channel.
SE4...SE0
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
BIT
FUNCTION
Dedicated Mic PCM in channel
Modem line codec support
Bass and treble control
Simulated stereo (mono to stereo)
Headphone out support
Loudness (bass boost) support
18-bit DAC resolution
20-bit DAC resolution
18-bit ADC resolution
20-bit ADC resolution
Wolfson Microelectronics 3D enhancement
PD Rev 4.5 July 2008
∞
VALUE ON
Production Data
dB.
WM9705
11000
0
0
0
0
1
0
1
0
1
0
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