isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 17

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

The minimum resistance when using the VREF
circuit of Figure 9 is 600 ; when using the VREF
output pin it is 200k
Figure 10b. AC-coupled Input with DC Bias
Single-ended Operation
Single-ended signals may be connected to the ispPAC20
input and one of the two differential ispPAC20 outputs
can be used to drive single-ended circuitry. So, in addi-
tion to fully differential I/O, either the input, output or both
may be used single-ended.
Single-ended Input . To connect the ispPAC20 differen-
tial input to a single-ended signal, one of the differential
inputs needs to be connected to a DC bias, preferably
VREF
(as in Figure 10b) or have a DC bias equal to the DC level
of the other input. Since the input voltage is defined as
V
information is only present on one input, the other being
connected to a voltage reference.
Single-ended Output . Connecting the output to a single-
ended circuit is simpler still. Simply connect one-half of
the differential output, but not the other. Either output
conveys the signal information, just at half the magnitude
of the differential output. The DC level of the single-
ended output will be VREF
aspect of the FilSum PACblock. If the load is not AC
coupled and is at a DC potential other than VREF
load draws a constant current. Using one of the differen-
tial outputs halves the available output voltage swing
(3V
is the same whether driving differentially or single-ended,
Theory of Operation (Continued)
IN+
V
PP
V
- V
IN+
IN-
OUT
versus 6V
IN-
, the common mode level is ignored. The signal
. The input signal must either be AC coupled
R
VREF
C
C
IN
IN
IN
OUT
PP
) and since the output current capacity
(as discussed earlier).
OUT
due to the re-referencing
OUT
OUT
buffer
, the
OUT
17
a single output can drive twice the load as the differential
output (150 vs. 300 or 2000pF vs. 1000pF). If the load
requires DC current, the amount available for voltage
swing is reduced. The output is capable of 10mA, so any
DC current raises the minimum allowable load imped-
ance.
Noise vs. Gain
Noise gain is the gain of a circuit configuration to its
combined input-referred circuit noise. The noise gain of
an inverting op amp circuit is:
In this case, the noise gain of the circuit increases
proportionally to the circuit gain.
A FilSum PACblock contains an input amplifier stage
followed by an output amplifier. In this way it can be
viewed as a system, with each of the components having
its own contribution to the overall noise as shown in
Figure 11. Both the output amplifier noise (N
amplifier noise (N
mance, but the contribution due to the output amplifier
dominates except at input gains near 10. The result is that
the SNR of a FilSum PACblock is nearly constant versus
gain. This is different than the behavior predicted by
Equation 9.
Figure 11. Multistage ispPAC Noise Diagram
There is a few dB decrease in SNR as the gain ap-
proaches 10. This characteristic implies the input amplifier
noise contribution is approaching that of the op amp. As
the gain of the input amplifier nears 10, its noise contribu-
tion in Equation 10a (N
If N
Noise
2
/G
Output
N 1
1
Stage One
Specifications ispPAC20
> 3·N
Gain
G 1
Noise
1
=
1
, then
) contribute to the overall noise perfor-
1
+
Closed
Voltage
1
) approaches that of the op amp
Loop
G
N 2
G 2 = Constant
2
Stage Two
N
Voltage
2
G 2
+
Gain
2
) and input
(10a)
(10b)
(9)