isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 24

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

JTAG User Bits
There are a number of user-configured E
control various aspects of ispPAC operation and can all
be accessed in either the pull-down menus or directly in
the schematic design entry screen of the PAC-Designer
software. See the online help associated with the
ispPAC20 in PAC-Designer for more details of how to set/
program various operation modes. The list of control E
bits available is given in Table 5.
Table 5. JTAG User Configuration Bits
PCMode1, 2
WCMode
CP1Buffer
UES1-7
SRE
ESF
EnCMVin1, 2 Enable External CMV Ref
Theory of Operation (Continued)
CPOut
DSthru
DisTDO
CPHyst
Symbol
Polarity Control Mode
Comparator Output Disable
Direct Serial Pass-Thru
Comparator Hysteresis
Disable TDO
Slew Rate Enhancement
Electronic Security Fuse
Window Compare Mode
Comparator 1 Latch Enable
User Electronic Signature
Name
Used to enable the serial, JTAG/Direct mode. Enables addressing of DAC
directly from the serial latches instead of the E
the DMode pin. Overridden itself by the ENSPI mode pin (high).
Used to disable the TDO output, or in other words place it in permanent
high-impedance output mode. This is done to reduce unnecessary on-chip
perturbation of the analog circuitry while changing the DAC codes in either
the JTAG/E
high and the DAC is in SPI mode. Note that TDO is disabled at certain times
even when the DisTDO bit is not set.
Causes output of Comparator 1 (CP1) to be latched into a D-flip-flop before
being output. Latch is updated by clocking the PC input pin.
Normally on, this bit enhances the slew rate capability of IA4. Normally this
is of greatest benefit in such applications as voltage controlled oscillators
where an improvement in non-sinusoidal waveform generation is desired.
Has no effect on THD of normal signals, but can still be disabled if output
needs to be matched exactly to the characteristics of IA1-3.
Setting this bit causes all subsequent readouts of the device configuration to
be disabled (JTAG Verify commands). Can be reset by performing a JTAG
user bulk erase command and reprogramming the device. This feature is
used to prevent unauthorized readout of the device’s configuration.
Enables an external input reference to determine the output common-mode
voltage of OA1 and/or OA2 instead of the normally-used 2.5V from on-chip.
Used to enable comparator hysteresis mode for both comparators (47mV).
Selected in PAC-Designer by double clicking on the hysteresis symbol in
between the two comparators or by using the edit symbol dialog.
Used to control the various modes of PC (polarity control) digital input pin
function. These include simple logic control of IA4’s gain polarity, a blocking
of the PC pin input altogether, an oscillator flip-flop control mode and gating
of the oscillator flip-flop mode, and direct connection to CP1OUT.
Used to enable either XOR or FF output mode on the Window output pin.
Disables all three comparator-related outputs (CP1, CP2 and Window)
placing them in a high impedance state. The purpose of the option is to
allow quieter operation of comparators (less effect on other analog circuitry)
when their outputs are only required for on-chip operation.
These bits are available to store information about an individual device in
on-chip E
performance data or other classification data could be stored and later
retrieved to identify some unique property associated by the user with the
device.
2
bits that
2
configuration memory. For example, the configuration code,
2
2
24
or JTAG/Direct modes. Has no effect on TDO when ENSPI is
Specifications ispPAC20
Description
2
cells. Overrides the effect of