wm8802scft/v Wolfgang Knap, wm8802scft/v Datasheet - Page 38

• Manufacturer Part Number: wm8802scft/v
• Description: Digital Audio Interface Transceiver
• Manufacturer: Wolfgang Knap

WM8802
Table 17 Relationship between Register Input/Output Contents and CCB Addresses
Figure 30 Input Timing Chart (Normal, Low Clock)
w
REGISTER INPUT/OUTPUT
Function setting data input
Interrupt data output
CS data output
Pc data output
CS data input
fs data output
DO
CE
CL
DI
CONTENTS
B0
Hi-Z
B1
DATA WRITE METHOD
Input is performed in the following sequence: CCB addresses of A0 to A3 and B0 to B3, chip
addresses of DI0 and DI1, command addresses of DI4 to DI7 and data of DI8 to DI15. DI2 and DI3
are reserved for the system and should always be set to "0".
For the chip addresses, DI0 corresponds to CAL (low-order) and DI1 corresponds to CAU (high-
order).
DATA READ METHOD
Read data is output from DO. DO is in the high impedance state when CE is Low and begins
outputting at the rising edge of CE after the register address is recognised. DO then returns to the
high impedance state at the falling edge of CE.
If DO outputs using multiple WM8802 units are to be shared the DO outputs of the WM8802 can be
set to in a high impedance state using DOEN, This will prevent any misreading of registers from an
unselected device.
INPUT/OUTPUT TIMINGS
B2
write
write
read
read
read
read
R/W
B3
A0
ADDRESS
A1
0xEC
0xED
0xEA
0xEB
0xE8
0xE9
CCB
A2
A3
B0
0
1
0
1
0
1
DI0
B1
0
0
1
1
0
0
DI1
DI2
B2
0
0
0
0
1
1
DI3
B3
1
1
1
1
1
1
DI4
DI5
A0
0
0
0
0
0
0
….
DI15
A1
1
1
1
1
1
1
PP Rev 1.1 April 2004
Product Preview
A2
1
1
1
1
1
1
A3
1
1
1
1
1
1
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