rt9238 ETC-unknow, rt9238 Datasheet - Page 12

• Manufacturer Part Number: rt9238
• Description: Vrm 8.5 Pwm And Triple Linear Power System Controller
• Manufacturer: ETC-unknow

RT9238
Fault Protection
All four outputs are monitored and protected against
extreme overload. The chip’s response to an output
overload is selective, depending on the faulting
output.
An over-voltage on V
outputs 1, 2, and 3, and latches the IC off. An under-
voltage on V
over-current event on output 1, or an under-voltage
event on output 2 or 3, increments the respective
fault counters and triggers a shutdown of outputs 1,
2, and 3, followed by a soft-start re-start. After three
consecutive fault events on either counter, the chip is
latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also
reset by a successful start-up of all the outputs.
Fig.3 shows a simplified schematic of the fault logic.
The over-current latches are set dependent upon the
states of the over-current (OC1), output 2 and 3
under-voltage (UV2, UV3) and the soft-start signals
(SS13, SS24). Window comparators monitor the SS
pins and indicate when the respective C
fully charged to above 4.0V (UP signals). An under-
voltage on either linear output (VSEN2, VSEN3, or
www.richtek-ic.com.tw
12
3.0V
10V
0V
0V
T0
T1
SS24
ATX3.3V
OUT4
ATX5V
ATX12V
Fig.3 Soft-start Interval
T2
V
OUT4
output latches the IC off. A single
T3
(1.8V)
OUT1
TIME
V
T4T5
VTTPG
OUT3
PGOOD
SS13
output (FB1) disables
(1.5V)
V
OUT1
V
OUT2
(1.65V)
SS
(1.2V)
pins are
Preliminary
VSEN4) is ignored until the respective UP signal
goes high. This allows V
without fault at start-up. Following an over-current
event (OC1, UV2, or UV3 event), bringing the SS24
pin below 0.8V resets the over-current latch and
generates a soft-started ramp-up of the outputs 1, 2,
and 3.
OUT1 Over-Voltage Protection
During operation, a short across the synchronous
PWM upper MOSFET (Q1) causes V
increase. When the output exceeds the over-voltage
threshold of 115% of DACOUT, the over-voltage
comparator trips to set the fault latch and turns the
lower MOSFET (Q2) on. This blows the input fuse
and reduces V
A separate over-voltage circuit provides protection
during the initial application of power. For voltages on
the VCC pin below the power-on reset (and above
~4V), the output level is monitored for voltages above
1.3V. Should FB1 exceed this level, the lower
MOSFET, Q2, is driven on.
Over-Current Protection
All outputs are protected against excessive over-
currents. The PWM controller uses the upper
SS13
SS24
UV3
OC1
UV4
UV2
OV
0.8V
4V
4V
Fig.4 Fault Logic-simplified Schematic
SS13UP
_
_
_
SS24UP
OUT1
LATCH
S
R
.
OC
Q
LATCH
R
S
OC
POR
OUT3
COUNTER
Q
R
and V
COUNTER
DS9238-01 July 2001
OUT4
INHIBIT 1,2,3
R
FAULT
LATCH
S
R
to increase
SSDOWN
Q
Q
OUT1
FAULT
to