zl2006 Intersil Corporation, zl2006 Datasheet - Page 17

• Manufacturer Part Number: zl2006
• Description: Adaptive Digital Dc-dc Controller With Drivers And Current Sharing
• Manufacturer: Intersil Corporation

5.4 Start-up Procedure
The ZL2006 follows a specific internal start-up
procedure after power is applied to the VDD pin. Table
10 describes the start-up sequence.
If the device is to be synchronized to an external clock
source, the clock frequency must be stable prior to
asserting
approximately 5-10 ms to check for specific values
stored in its internal memory. If the user has stored
values in memory, those values will be loaded. The
device will then check the status of all multi-mode pins
and load the values associated with the pin settings.
Once this process is completed, the device is ready to
accept commands via the I
device is ready to be enabled. Once enabled, the device
requires approximately 2 ms before its output voltage
may be allowed to start its ramp-up process. If a soft-
start delay period less than 2 ms has been configured
(using DLY pins or PMBus commands), the device
will default to a 2 ms delay period. If a delay period
greater than 2 ms is configured, the device will wait for
the configured delay period prior to starting to ramp its
output.
After the delay period has expired, the output will
begin to ramp towards its target voltage according to
the pre-configured soft-start ramp time that has been
set using the SS pin. It should be noted that if the EN
pin is tied to VDD, the device will still require approx
5-10 ms before the output can begin its ramp-up as
described in Table 10 below.
Table 10. ZL2006 Start-up Sequence
Step #
1
2
3
4
5
the
Internal Memory
Pre-ramp Delay
Multi-mode Pin
Power Applied
Device Ready
Step Name
EN
Check
Check
17
pin.
2
C/SMBus interface and the
The
Input voltage is applied to the ZL2006’s VDD
pin
The device will check for values stored in its
internal memory. This step is also performed
after a Restore command.
The device loads values configured by the
multi-mode pins.
The device is ready to accept an enable signal.
The device requires approximately 2 ms
following an enable signal and prior to ramping
its output. Additional pre-ramp delay may be
configured using the Delay pins.
device
requires
Description
ZL2006
5.5 Soft Start Delay and Ramp Times
It may be necessary to set a delay from when an enable
signal is received until the output voltage starts to ramp
to its target value. In addition, the designer may wish
to precisely set the time required for V
its target value after the delay period has expired.
These features may be used as part of an overall inrush
current management strategy or to precisely control
how fast a load IC is turned on. The ZL2006 gives the
system designer several options for precisely and
independently controlling both the delay and ramp time
periods.
The soft-start delay period begins when the EN pin is
asserted and ends when the delay time expires. The
soft-start delay period is set using the DLY (0,1) pins.
Precise ramp delay timing reduces the delay time
variations but is only available when the appropriate
bit in the MISC_CONFIG register has been set. Please
refer to Application Note AN33 for details.
The soft-start ramp timer enables a precisely controlled
ramp to the nominal V
delay period has expired. The ramp-up is guaranteed
monotonic and its slope may be precisely set using the
SS pin.
The soft start delay and ramp times can be set to
standard values according to Table 11 and Table 12
respectively.
PMBus traffic during this period)
Depends on input supply ramp
Approx 5-10 ms (device will
OUT
ignore an enable signal or
Approximately 2 ms
value that begins once the
Time Duration
time
December 15, 2010
⎯
OUT
FN6850.1
to ramp to