ox16c954 ETC-unknow, ox16c954 Datasheet - Page 20

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

Note 10:
Offset values not listed in the table are reserved for future use and must not be used.
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
Register
Name
MDM
PIDX
NMR
GDS
DMS
ACR
CPR
TCR
CKS
FCH
REV
CSR
RFC
CKA
RTL
FCL
TTL
ID1
ID2
ID3
The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR.
Offset
SPR
0x0C
0x0D
0X0F
0X10
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
0x11
0x12
0x13
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
inactive
Enable
FCR[7]
Status
TxRdy
Bit 7
Addit-
Tx 1x
Mode
Force
ional
Unused
Table 7: Indexed Control Register Set
Indexed Control Register Set
Tx CLK
inactive
Enable
FCR[6]
RxRdy
Select
Bit 6
Force
Read
ICR
Reserved
Hardwired Port Index ( 0x00, 0x01, 0x02, 0x03 respectively )
Unused
5 Bit “integer” part of
Unused
clock prescaler
reset the UART (Except the CKS and CKA registers)
SChar 4
BDOUT
on DTR
Trigger
Enable
FCR[5]
Bit 5
9
Level
950
th
Automatic Flow Control Lower Trigger Level (0-127)
Automatic Flow Control Higher Trigger level (1-127)
Bit
Writing 0x00 to this register will
Hardwired revision byte (0x04)
Transmitter Interrupt Trigger Level (0-127)
Hardwired ID byte 1 (0xC9)
Receiver Interrupt Trigger Level (1-127)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0x54)
SChar 3
Unused
DTR 1x
Tx CLK
FCR[4]
Bit 4
DTR definition and
9
th
Bit
Unused
control
CLKSEL
SChar 2
Wakeup
disable
FCR[3]
sys-clk
Bit 3
pin for
9
Rx 1x
Mode
Use
th
DCD
Bit
SChar 1
RI edge
Trailing
Control
Enable
disable
FCR[2]
Unused
Bit 2
9
signal
4 Bit N-times clock
Invert
Auto
DSR
Flow
selection bits [3:0]
DTR
th
Bit
3 Bit “fractional” part of
clock prescaler
9
Wakeup
Disable
internal
tx clock
OX16C954 rev B
disable
FCR[1]
th
TxRdy
Bit 1
status
Invert
-bit Int.
( R )
En.
Tx
DSR
Clock Sel[1:0]
Receiver
Wakeup
Disable
rx clock
disable
FCR[0]
internal
Enable
RxRdy
Status
Bit 0
status
Good
Invert
Data
Page 20
9 Bit
( R )
Rx
CTS