isplsi2032v-80lt44 Lattice Semiconductor Corp., isplsi2032v-80lt44 Datasheet - Page 2

isplsi2032v-80lt44

Manufacturer Part Number

isplsi2032v-80lt44

Description

3.3v High Density Programmable Logic

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI2032V-80LT44.pdf (12 pages)

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Figure 1. ispLSI 2032V Functional Block Diagram

The device also has 32 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, output or bi-

directional I/O pin with 3-state control. The signal levels

are TTL compatible voltages and the output drivers can

source 4 mA or sink 8 mA. Each output can be pro-

grammed independently for fast or slow output slew rate

to minimize overall output switching noise. Device pins

can be safely driven to 5 Volt signal levels to support

mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two

ORPs are connected together to make a Megablock (see

Figure 1). The outputs of the eight GLBs are connected

to a set of 32 universal I/O cells by the ORP. Each ispLSI

2032V device contains one Megablock.

The GRP has as its inputs the outputs from all of the GLBs

and all of the inputs from the bi-directional I/O cells. All of

these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2032V device are selected using the

dedicated clock pins. Three dedicated clock pins (Y0, Y1,

Y2) or an asynchronous clock can be selected on a GLB

Functional Block Diagram

TDO/IN 1

GOE 0

TMS/NC

TDI/IN 0

Note:

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

ispEN

*Y1 and RESET are multiplexed on the same pin

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

Global Routing Pool

(GRP)

basis. The asynchronous or Product Term clock can be

generated in any GLB for its own clock.

In addition to the standard output configuration, the

outputs of the ispLSI 2032V are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. When this fuse is erased (JEDEC “1”),

the output is configured as a totem-pole output. When

this fuse is programmed (JEDEC “0”), the output is

configured as an open-drain. The default configuration

when the device is in bulk erased state is totem-pole

configuration. The open-drain/totem-pole option is se-

lectable through the ispDesignEXPERT software tools.

Programmable Open-Drain Outputs

Specifications ispLSI 2032V

Blocks (GLBs)

Generic Logic

TCK/Y2

Y1*

0139B/2032V

I/O 31

I/O 30

I/O 29

I/O 28

I/O 27

I/O 26

I/O 25

I/O 24

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 16

isplsi2032v-80lt44 Lattice Semiconductor Corp., isplsi2032v-80lt44 Datasheet - Page 2

isplsi2032v-80lt44

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