m52d32321a Elite Semiconductor Memory Technology Inc., m52d32321a Datasheet - Page 5

• Manufacturer Part Number: m52d32321a
• Description: 512k X 32bit X 2banks Mobile Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note:
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Refresh period (4,096 rows)
Number of valid output data
1.
2.
3.
4.
5.
6.
Output
10.6K
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
A maximum of eight consecutive AUTO REFRESH commands (with t
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6 μ s.)
A new command may be given t
Parameter
(Fig.1) DC Output Load circuit
@ Operating
@ Auto refresh
Parameter
1.8V
13.9K
20 pF
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
RFC
CAS latency=3
CAS latency=2
after self refresh exit.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
RFC
CDL
RDL
BDL
CCD
REF
(V
(min)
(min)
DD
(min)
(min)
(min)
(max)
(min)
(max)
(min)
(min)
(min)
(min)
=1.8V
±
0.1V,T
A
0.9 x V
= 0 C
22.5
14
20
45
65
65
-7
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
Output
° ~ 70 C
Value
DDQ
Version
DDQ
DDQ
RFCmin
/ 0.2
100
° )
64
1
2
1
1
2
1
(Fig.2) AC Output Load Circuit
) can be posted to any given SDRAM, and
Z0=50
-10
20
30
30
50
90
90
Revision : 1.6
Publication Date : May 2009
M52D32321A
Vtt =0.5x VDDQ
20 pF
50
Unit
CLK
CLK
CLK
CLK
ms
ns
ns
ns
ns
us
ns
ns
ea
Unit
ns
V
V
V
Note
5/30
1,6
1
1
1
1
1
2
2
2
3
5
4