f25l32qa Elite Semiconductor Memory Technology Inc., f25l32qa Datasheet
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f25l32qa
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f25l32qa Summary of contents
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... F25L32QA –100PHG 100MHz GENERAL DESCRIPTION The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. ...
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... SOIC HOLD / SIO SIO 1 Elite Semiconductor Memory Technology Inc. (Preliminary F25L32QA HOLD / SIO SCK SIO 0 SCK SIO SIO 2 Publication Date: Jan ...
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... SCK and read data or status from the device on the falling edge of SCK (for Quad mode). To provide power. Page Address Memory Array Page Buffer Y-Decoder Byte Address Latch / Counter Serial Interface HOLD (SIO ) (SIO ) (SIO ) (SIO ) F25L32QA Functions Publication Date: Jan. 2009 Revision: 0.2 3/42 ...
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... ESMT SECTOR STRUCTURE Table 1: F25L32QA Sector Address Table Block Sector 1023 63 : 1008 1007 62 : 992 991 61 : 976 975 60 : 960 959 59 : 944 943 58 : 928 927 57 : 912 911 56 : 896 895 55 : 880 879 54 : 864 863 53 : 848 847 52 : 830 831 51 : 816 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32QA Sector Address Table – Continued I Block Sector 815 50 : 800 799 49 : 784 783 48 : 768 767 47 : 752 751 46 : 736 735 45 : 720 719 44 : 704 703 43 : 688 687 42 : 672 671 41 : 656 655 40 : 640 639 39 : 624 623 38 : 608 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32QA Sector Address Table – Continued II Block Sector 607 37 : 592 591 36 : 576 575 35 : 560 559 34 : 544 543 33 : 528 527 32 : 512 511 31 : 496 495 30 : 480 479 29 : 464 463 28 : 448 447 27 : 432 431 26 : 416 415 25 : 400 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32QA Sector Address Table – Continued III Block Sector 399 24 : 384 383 23 : 368 367 22 : 352 351 21 : 336 335 20 : 320 319 19 : 304 303 18 : 288 287 17 : 272 271 16 : 256 255 15 : 240 239 14 : 224 223 13 : 208 207 12 : 192 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32QA Sector Address Table – Continued IV Block Sector 191 11 : 176 175 10 : 160 159 9 : 144 143 8 : 128 127 7 : 112 111 Elite Semiconductor Memory Technology Inc. (Preliminary) Sector Size Address range ...
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... A “0” indicates the device is ready for the next valid operation. Auto Address Increment (AAI) The Auto-Address-Increment-Programming-Status bit provides status on whether the device is in AAI Programming mode or Page Program mode. The default at power up is Page Program mode. F25L32QA Default at Read/Write Power- ...
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... QE should never be set to “1” during standard and Dual SPI operation if the WP and HOLD pins are tied directly to the Elite Semiconductor Memory Technology Inc. (Preliminary) Table 3: F25L32QA Block Protection Table Status Register Bit BP2 BP1 BP0 ...
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... ctive Figure 1: HOLD Condition Waveform WRITE PROTECTION F25L32QA provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. When the ...
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... ESMT INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L32QA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first ...
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... Bus Cycle OUT2 OUT3 F25L32QA 1~3 Bus Cycle OUT IN OUT IN OUT 40H X 16H - - 00H Hi-Z X 8CH X Hi-Z 01H Hi-Z X 15H ...
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... IN2 IN3 , OUT5 ) before D 0 Publication Date: Jan. 2009 Revision: 0.2 F25L32QA , and then input IN 14/42 ...
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... ADD. ADD. ADD. X MSB MSB F25L32QA - must remain active N+1 N+2 N+3 N ...
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... Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence Dummy ADD. ADD. ADD. MSB HIGH IMPENANCE F25L32QA switches from In put to Ouput ...
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... switches from In put to Ouput OUT OUT OU T OUT N N+1 N+2 N+3 N Publication Date: Jan. 2009 Revision: 0.2 F25L32QA OUT OUT N+3 N+4 OUT 17/42 ...
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... Quad Output sequence ADD. ADD. MSB MSB HIGH IMPENANCE HIGH IMPENANCE HIGH IMPENANCE F25L32QA 4142 switches from Input to Ouput Dummy DD ...
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... IO switches from Input to Ouput 0 Dummy N+1 N OUT OUT OUT IO switches from Input to Oup N+1 N OUT OU T Publication Date: Jan. 2009 Revision: 0.2 F25L32QA 19/42 ...
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... After the Page Program cycle has 7 0 finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 10 for the Page Program sequence. F25L32QA Publication Date: Jan. 2009 Revision: 0.2 20/42 ...
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... Register-2 must be set “1”. The other function descriptions are as same as standard Page Program. See Figure 11 for the Quad Page Program sequence ADD. ADD. A DD. MSB F25L32QA 3839 ...
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... The 8-bit command, 80H, disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output Software Status Register data during AAI WORD programming (refer to Figure 13). Figure 13: Disable SO as Hardware during AAI Programming F25L32QA -A ] with A =0; the second byte ...
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... ESMT Figure 14: AAI Word Program Sequence with Hardware End of Write Detection Figure 15: AAI Word Program Sequence with Software End of Write Detection Elite Semiconductor Memory Technology Inc. (Preliminary) F25L32QA Publication Date: Jan. 2009 Revision: 0.2 23/42 ...
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... SPI instruction. See Figure 16 for the Mode Bit Reset instruction. Mode bit Reset for Dual I – “AxH”, the device will not recognize any standard SPI Publication Date: Jan. 2009 Revision: 0.2 F25L32QA – 24/42 ...
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... Erase cycle. See Figure 18 for the Sector Erase sequence Address bits ADD. MSB MSB HIGH IMPENANCE F25L32QA - Most Significant address) are must be driven high before the IL IH for the completion of the ...
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... RDSR instruction sequence HIGH IMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB Status Register - Data Out F25L32QA for the completion of the internal self-timed Publication Date: Jan. 2009 Revision: 0.2 26/42 ...
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... CE must be driven high before the WRDI instruction is executed MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. F25L32QA Publication Date: Jan. 2009 Revision: 0.2 27/42 ...
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... WRSR command will ignore the input data and lock down the secured OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6. F25L32QA ) prior to the low-to-high transition of the IH Stauts Register - 2 ...
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... RES1 The instruction is executed while an Erase, Program or WRSR cycle is in progress is ignored and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status of OTP. F25L32QA ). See Figure 25 for the Deep Power SB1 T DP Deep Power Down Current ...
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... In secured OTP mode & lock down (OTP_lock =1) T RES1 Standby Current (I ) SB2 Electronic-Signature Data Out MSB Deep Power Down Current (I ) SB2 Electronic Signature Data 15H 35H 75H Publication Date: Jan. 2009 Revision: 0.2 F25L32QA T RES2 Standby Current 30/42 ...
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... HIGH IMPENANCE SO Figure 28: JEDEC Read-ID Sequence Manufacturer’s ID Elite Semiconductor Memory Technology Inc. (Preliminary) F25L32QA. The instruction sequence is shown in Figure 28. The JEDEC Read ID instruction is terminated by a low to high transition any time during data output other instruction, the 8-bit command is issued after executing the JEDEC Read-ID ...
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... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L32QA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, ...
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... V 1 µ F25L32QA Value Unit ℃ Test Condition CE =0 SO=open =0 SO=open =0 SO=open =0 SO=open ...
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... Publication Date: Jan. 2009 Revision: 0.2 F25L32QA Unit µs µs Maximum Fast 100 MHz Unit Min Max 100 MHz 100 ns 9 ...
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... Symbol 2 Typ Max T 90 300 1 100 100,000 - 20 - F25L32QA Fast 86 MHz Fast 100 MHz Min Max Min Max 1.8 1.8 Unit Cycles Years Publication Date: Jan. 2009 Revision: 0.2 ...
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... ESMT Figure 30: Serial Input Timing Diagram Figure 31: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. (Preliminary) F25L32QA Publication Date: Jan. 2009 Revision: 0.2 36/42 ...
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... V CC Program, Erase and Write command is ignored CE must track V CC (min) T Reset VSL State PUW Threshold WI Symbol Min. T 200 VSL T PUW F25L32QA Read command Device is fully is allowed accessible Time Max. Unit Publication Date: Jan. 2009 Revision: 0.2 37/42 ...
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... Figure 34: AC Input/Output Reference Waveforms Figure 35: A Test Load Example Elite Semiconductor Memory Technology Inc. (Preliminary) Input timing reference level 0.7VCC Measurement 0.3VCC Note : Input pulse rise and fall time are <5ns F25L32QA Output timing reference level AC 0.5VCC Level Publication Date: Jan. 2009 Revision: 0.2 38/42 ...
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... L L1 DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1.27 BSC 0.050 BSC 1.27 1.37 1.47 0.050 0.054 ° 0 ° 0 ° 8 --- Publication Date: Jan. 2009 Revision: 0.2 F25L32QA Max 0.319 0.212 0.032 0.058 ° 8 --- 39/42 ...
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... GAUGE PLANE L DETAIL "X" "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 10.30 BSC 0.406 BSC 7.50 BSC 0.295 BSC 0.40 --- 1.27 0.016 1.27 BSC 0.050 BSC ° 0 ° 0 ° 8 --- Publication Date: Jan. 2009 Revision: 0.2 F25L32QA Max --- 0.050 ° 8 --- 40/42 ...
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... Add 16-pin SOIC package 2. Add the specification of 86MHz 3. Modify the size of OTP security sector 2008.01.13 4. Modify typo error 5. Modify headline and the specification Delete T and the rating of Temperature Under Bias BP1 F25L32QA Description Original CE Publication Date: Jan. 2009 Revision: 0.2 41/42 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. (Preliminary) Important Notice F25L32QA Publication Date: Jan. 2009 Revision: 0.2 42/42 ...