m52d64322a Elite Semiconductor Memory Technology Inc., m52d64322a Datasheet - Page 32
m52d64322a
Manufacturer Part Number
m52d64322a
Description
512k X 32 Bit X 4 Banks Mobile Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
1.M52D64322A.pdf
(46 pages)
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ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
D Q
*Note :
Elite Semiconductor Memory Technology Inc.
C L O C K
A 1 0 / A P
D Q M
B A 1
B A 0
W E
A D D R
C L = 2
C L = 3
C K E
C A S
R A S
C S
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
0
( A - Bank )
available after Row precharge. Last valid output will be Hi-Z (t
Row Active
R a
R a
1
t
2
R C D
3
( A - Bank )
Read
C a 0
4
5
Q a 0
6
Q a 1
Q a 0
* N o t e 2
7
( A - Bank )
Precharge
Q a 1
Q a 2
8
Q a 3
Q a 2
9
H I G H
Q a 3
10
Row Active
( A - Bank )
* N o t e 3
R b
R b
SHZ
11
) after the clock.
* N o t e 3
12
13
( A - Bank )
Write
Q b 0
C b 0
Q b 0
Publication Date: Jan. 2009
Revision: 1.4
14
Q b 1
Q b 1
15
Q b 2
Q b 2
M52D64322A
16
Q b 3
Q b 3
17
t
: D o n ' t C a r e
t
R D L
R D L
18
P r e c h a r g e
( A - B a n k )
32/46
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