m52s32321a Elite Semiconductor Memory Technology Inc., m52s32321a Datasheet - Page 2

• Manufacturer Part Number: m52s32321a
• Description: 512k X 32bit X 2banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Elite Semiconductor Memory Technology Inc.
CLK
CKE
A0 ~ A10
BA
L(U)DQM
CS
RAS
CAS
WE
Pin
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
ADD
CLK
LCKE
Name
CLK
LRAS
CKE
Bank Select
LCBR
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
CAS low.
LWE
Timing Register
RAS
LCAS
CAS
Programming Register
Data Input Register
Latency & Burst Length
Column Decoder
512K x 32
512K x 32
WE
L(U)DQM
LWCBR
Input Function
LDQM
Revision : 1.5
Publication Date : Jan. 2009
M52S32321A
LWE
LDQM
DQi
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