a290011tx-90f AMIC Technology Corporation, a290011tx-90f Datasheet - Page 2

• Manufacturer Part Number: a290011tx-90f
• Description: 128k X 8 Bit Cmos 5.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMIC Technology Corporation

The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
General Description
The A29001 is a 5.0 volt-only Flash memory organized as
131,072 bytes of 8 bits each. The A29001 offers the
128 Kbytes of data are further divided into seven sectors for
flexible sector erase capability. The 8 bits of data appear on
I/O
A29001 is offered in 32-pin PLCC, TSOP, sTSOP and PDIP
packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write
or erase operations. However, the A29001 can also be
programmed in standard EPROM programmers.
The A29001 has the first toggle bit, I/O
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O
A29001 has a second toggle bit, I/O
the addressed sector is being selected for erase. The
A29001 also offers the ability to program in the Erase
Suspend mode. The standard A29001 offers access times
of 55, 70 and 90 ns allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable (
and output enable (
RESET
Features
(December, 2004, Version 1.3)
0
- 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
5.0V ± 10% for read and write operations
Access times:
- 55/70/90 (max.)
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
Flexible sector architecture
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
- Embedded Program algorithm automatically writes
- I/O
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
the entire chip or any combination of designated
sectors and verify the erased sectors
and verifies bytes at specified addresses
7
function, but it is not available on A290011. The
while the addresses are input on A0 to A16. The
OE
) controls.
CE
2
), write enable ( WE )
, to indicate whether
6
, which indicates
6
toggle bit, the
1
The A29001 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times
the program pulse widths and verifies proper program
margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O
and I/O
cycle has been completed, the device is ready to read
array data or accept another command.
Typical 100,000 program/erase cycles per sector
Industrial operating temperature range: -40°C to +85°C
for – U
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
- Superior inadvertent write protection
- Provides a software method of detecting completion
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data
Hardware reset pin (
- Hardware method to reset the device to reading array
Package options: 32-pin P-DIP, PLCC, TSOP or
Data
128K X 8 Bit CMOS 5.0 Volt-only,
supply Flash memory standard
data (not available on A290011)
of program or erase operations
sTSOP (Forward type)
from, or program data to, a non-erasing sector, then
resumes the erase operation
6
Polling and toggle bits
(toggle) status bits. After a program or erase
A29001/290011 Series
Boot Sector Flash Memory
AMIC Technology, Corp.
RESET
)
7
(
Data
Polling)