f25l32pa Elite Semiconductor Memory Technology Inc., f25l32pa Datasheet - Page 3

• Manufacturer Part Number: f25l32pa
• Description: 3v Only 32 Mbit Serial Flash Memory With Dual
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Elite Semiconductor Memory Technology Inc.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
SO / SIO
SI / SIO
Symbol
HOLD
SCK
V
WP
V
CE
DD
SS
0
1
Serial Data Input Output 0
Serial Data Input Output 1
High Voltage
CE
Generator
Serial Data Output /
Serial Data Input /
Power Supply
Write Protect
Chip Enable
Serial Clock
Pin Name
Ground
SCK
Hold
Register
Command and Conrol Logic
Status
Latch / Counter
Page Address
(SIO
Serial Interface
SI
0
Latch / Counter
)
Byte Address
(SIO
SO
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard mode). / Bidirectional IO pin to
transfer commands, addresses or data serially into the device on the rising
edge of SCK and read data or status from the device on the falling edge of
SCK(for Dual mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual mode).
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register.
To temporality stop serial communication with SPI flash memory without
resetting the device.
To provide power.
1
)
WP
Page Buffer
Y-Decoder
Memory
HOLD
Array
Functions
Publication Date: Mar. 2009
Revision: 1.0
F25L32PA
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