LMH1982SQ National Semiconductor Corporation, LMH1982SQ Datasheet - Page 3

• Manufacturer Part Number: LMH1982SQ
• Manufacturer: National Semiconductor Corporation

Connection Diagram
Pin Descriptions
Notes
1. To control reference selection via the REF_SEL input pin instead of the I
2. To override reference control via pin 6 and instead use pin 6 as an logic pulse input for output alignment initialization, program PIN6_OVRD = 1 (register 02h).
Consequently, reference selection must be controlled via I
3. SDA and SCL pins each require a 4.7kΩ (typ.) pull-up resistor to the V
4. To control mode selection via the GENLOCK input pin instead of the I
2, 10, 18, 22, 26, 30
3, 21, 27, 28, 32
Pin No.
19, 20
23, 24
11
12
13
14
15
16
17
25
29
31
1
4
5
6
7
8
9
–
HD_CLK, HD_CLK
SD_CLK, SD_CLK
VC_FREERUN
I
2
GENLOCK
NO_LOCK
Pin Name
REF_SEL
C_ENABLE
NO_REF
HREF_A
VREF_A
HREF_B
VREF_B
RESET
VCXO
DV
GND
DAP
SDA
SCL
TOF
LPF
V
DD
DD
2
C, and the TOF_INIT bit (register 0Ah) will be ignored.
I/O
I/O
O
O
O
O
O
O
–
–
–
–
2
I
I
I
I
I
I
I
I
I
I
I
DD
C interface (default), program I
Top View
2
supply.
C interface (default), program I
3
Signal Level
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
Analog
Supply
Supply
Supply
Supply
LVDS
LVDS
I
I
2
2
C
C
2
C_GNLK = 0 (register 00h).
2
C_RSEL = 0 (register 00h).
30052402
Die Attach Pad (Connect to GND)
Free Run Control Voltage Input
Ground
3.3V Supply
H sync Input, Reference A
V sync Input, Reference A
Reference Select
H sync Input, Reference B
V sync Input, Reference B
2.5V Supply
I
I
I
Mode Select
Device Reset
Reference Status Flag
Lock Status Flag
HD Clock Output
SD Clock Output
Top of Frame Pulse
VCXO Clock Input
VCXO PLL Loop Filter
2
2
2
C Data
C Clock
C Enable
3
3
Pin Description
4
1, 2
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