LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 7

• Manufacturer Part Number: LMK03000
• Manufacturer: National Semiconductor Corporation

t
t
t
t
t
t
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CS
CH
CWH
CWL
ES
CES
EWH
Note 4: See Section 3.5 for more current consumption / power dissipation information.
Note 5: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L
can be masked by the reference oscillator performance if the source is low power or noisy. The total PLL inband phase noise performance is the sum of L
(f) and L
performance is the sum of L
Note 6: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L
L
comparison frequency of the synthesizer. L
smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. L
masked by the reference oscillator performance if the source is low power or noisy.
Note 7: Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient temperature
and programmed state at which the device was when register R15 was programmed. The action of programming the R15 register, even to the same value,
activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum
allowable drift for continuous lock, then it will be necessary to reload the R15 register to ensure that it stays in lock. Regardless of what temperature the part was
initially programmed at, the ambient temperature can never drift outside the range of -40 °C
to be valid the programmed state of the device must not change after R15 is programmed.
Note 8: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically
varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB,
assuming the part is not reloaded. Re-programming R15 will run the frequency calibration routine for optimum phase noise.
Note 9: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock
distribution section only and is in RMS form addition to the jitter from the VCO.
Note 10: Specification is guaranteed by characterization and is not tested in production.
Note 11: Applies to GOE, LD, and SYNC*.
Note 12: Applies to uWireCLK, uWireDATA, and uWireLE.
Serial Data Timing Diagram
Data bits set on the DATA signal are clocked into a shift register, MSB first, on each rising edge of the CLK signal. On the rising
edge of the LE signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the
programming is complete the CLK, DATA, and LE signals should be returned to a low state.
Symbol
PLL_flat
(f) – 20log(N) – 10log(Fcomp). L
PLL_flat
(f). L
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Enable Set Up Time
Enable to Clock Set Up Time
Enable Pulse Width High
PLL_flicker
(f) can be masked by the reference oscillator performance if the source is low power or noisy. The total PLL inband phase noise
PLL_flicker
Parameter
(f) and L
PLL_flat
PLL_flat
PLL_flat
(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and Fcomp is the
(f) contributes to the total noise, L(f). To measure L
(f).
MICROWIRE Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
7
PLL_flicker
Conditions
≤
(f), which is dominant close to the carrier. Flicker noise has a 10
T
A
≤
PLL_flat
85 °C without violating specifications. For this specification
PLL_flicker
(f) the offset frequency, f, must be chosen sufficiently
PLL_flat
PLL_flicker
(10 kHz) - 20log(Fout / 1 GHz), where L
(f), of the PLL and is defined as: PN1Hz =
(f) it is important to be on the 10 dB/decade
Min
25
25
25
25
25
25
8
Typ
Max
PLL_flat
20211403
www.national.com
PLL_flicker
(f) can be
PLL_flicker
PLL_flicker
Units
ns
ns
ns
ns
ns
ns
ns
(f)