hsp50216 Intersil Corporation, hsp50216 Datasheet - Page 31

• Manufacturer Part Number: hsp50216
• Description: Four-channel Programmable Digital Downconverter
• Manufacturer: Intersil Corporation

ADD(2:0)
0
1
2
3
0
1
2
3
PINS
WR
WR
WR
WR
RD
RD
RD
RD
31
Indirect Write Holding Register, Bits 15:0.
Indirect Write Holding Register, Bits 31:16.
Indirect Write Address Register for Internal Target Register (Generates a write strobe to transfer contents of the
Write Holding Register into the Target Register specified by the Indirect Address, see also Table of Indirect Read
Address (IRA) Registers).
Indirect Read Address Register (Used to select the Read source of data - uses the same register as Direct
Address 2 but generates a read strobe (for RAMs and AGC) as needed instead of a write strobe).
Indirect Read, Bits 15:0.
Indirect Read, Bits 31:0f.
Read Register (FIFO) - Reads FIFO data from output section (This location reads output data in the order
loaded in Global Control Indirect Address Registers F820-F83F. The FIFO is automatically incremented to the
next data location at the end of each read).
Status Register
TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES
P(15:0)
15:12
11:6
5:2
1
0
Unused.
Read non-bus input pins (ENIx, RESET, SYNCI).
11 RESET (Note: This bit is inverted with respect to the RESET input pin).
10 ENIA.
9 ENIB.
8 ENIC.
7 ENID.
6 SYNCI.
Mask revision number.
Level detector integration done. Active high.
New FIFO output data available (used for polling mode vs interrupt mode) Active low.
HSP50216
REGISTER DESCRIPTION
BIT DESCRIPTION
August 17, 2007
FN4557.6