hsp50307 Intersil Corporation, hsp50307 Datasheet
hsp50307
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hsp50307 Summary of contents
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... Copyright Copyright Description The HSP50307 is a mixed signal burst QPSK Modulator for upstream CATV Applications. The HSP50307 demultiplexes and modulates a serial data stream onto an RF Carrier cen- tered between 8 and 15MHz. The signal spectrum is shaped with = 0.5 root raised cosine (RRC) digital fi ...
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... Negative supply for the cable interface. (P) AVDD I Positive supply for the cable interface (+9V analog). (P) MOD_OUT+ O Positive output drive pin for the cable interface. (A) MOD_OUT- O Negative output drive pin for the cable interface. (A) HSP50307 28 LEAD SOIC TOP VIEW MCLK 1 28 CCLK TXCLK 2 27 ...
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... I 3 wire interface clock. See Control Interface Section. (D) NOTE: (A) = analog, (D) = digital, (P) = power. Functional Description The HSP50307 is designed to transmit 256 KBPS data using QPSK modulation on a programmable carrier over 75 cable lines. The incoming 256 KBPS data is first demultiplexed into in-phase (I) and quadrature (Q) data streams ...
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... CCLK C_DATA D22 D21 C_EN FIGURE 3. CONTROL INTERFACE TIMING DIAGRAM HSP50307 Synthesizer The synthesizer generates the quadrature LO’s for modulating the baseband data to RF. The carrier frequency is phase locked to the reference clock (RCLK). The carrier frequency, F with a resolution of 32kHz. Equation 1 gives the relationship ...
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... Figure 4. Again, these specifications are met given a valid programmed mode. NOTE: The HSP50307 is sensitive to layout. Users must make sure the input signals do not couple back into the output signals. The performance of the HSP50307 is also sensitive to the decoupling capacitors between 1) QBBOUT and QBBIN and 2) IBBOUT and IBBIN ...
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... Output Gain Adjust Relative Accuracy Absolute Output Accuracy at Any Step QPSK Carrier Phase Noise at 10kHz Offset QPSK Carrier Phase Noise at 1kHz Offset QPSK Modulator Carrier Suppression QPSK I/Q Amplitude Imbalance QPSK I/Q Phase Imbalance QPSK Passband Amplitude Ripple HSP50307 MIN TYP 8 ...
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... C_EN Strobe Edge to CCLK TXCLK Period (256kHz) TXCLK High TXCLK Low TX_DATA Setup to TXCLK TX_DATA Hold from TXCLK HSP50307 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . .-65 Maximum Lead Temperature (Soldering 10s 300 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HSP50307 PART IS ACTIVE AGAIN RCLK ...