lc01707plf Sanyo Semiconductor Corporation, lc01707plf Datasheet - Page 10
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lc01707plf
Manufacturer Part Number
lc01707plf
Description
Fm Multiple Tuner Ic
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
1.LC01707PLF.pdf
(18 pages)
Acknowledge (Receive acknowledge)
Software reset
When the master generates the acknowledge clock pulse, the transmitter opens the SDA line. (SDA line enters the [H]
state.) When the acknowledge clock pulse is in the [H] state, the receiver sets the SDA line to [L] each time it receives
one byte (eight bits) data. When the master works as a receiver, the master informs the slave of the end of data by
omitting acknowledge at the end of data sent from the slave.
If the communication is interrupted (microcomputer reset, etc.), it is possible to communicate normally by entering the
below signals and resetting the CPU in software.
*These signal timings restore the communication after its interruption. The register setting is never reset.
*Software reset command is incompatible with I
Data output by
receiver
Data output by
transmitter
SDA
SCL
SCL from
master
START condition
S
START condition
S
1
2
1
ACK:acknowledgement
NACK:not acknowledgement
LC01707PLF
2
C-bus format.
7
2
8
Repeated START condition
Release the SDA line(HIGH)
9
ACK(master is transmitter)
NACK(master is receiver)
8
Sr
Clock pulse for ACK
STOP cindition
9
P
No.A1928-10/18