ak4589 AKM Semiconductor, Inc., ak4589 Datasheet
ak4589
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ak4589 Summary of contents
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... ASAHI KASEI The AK4589 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise ...
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... Serial µP I/F • Two Master Clock Outputs: 64fs/128fs/256fs/512fs TTL Level Digital I/F 2 4-wire Serial and I Operating Voltage: 4.75 to 5.25V with 5V tolerance Power Supply for output buffer: 2.7 to 5.25V 80pin LQFP Package (0.5mm pitch) AK4588 compatible w/o analog outputs MS0339-E-00 C Bus µP I/F for mode setting - 2 - [AK4589] 2004/09 ...
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... DEM DATT DEM Format DATT Converter DEM DATT SDOUT DEM DATT DEM SDIN1 SDIN2 SDIN3 DATT SDIN4 DEM DATT DEM - 3 - [AK4589] XTO Clock MCKO1 Generator MCKO2 LRCK2 Audio BICK2 I/F SDTO2 DAUX2 PDN I2C CSN CCLK Q-subcode µP I/F buffer CDTO CDTI INT0 ...
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... ASAHI KASEI Ordering Guide -10 ∼ +70°C AK4589VQ AKD4589 Evaluation Board for AK4589 Pin Layout 1 INT1 2 BOUT 3 TVDD 4 DVDD 5 DVSS 6 XTO 7 XTI 8 TEST3 9 MCKO2 10 MCKO1 11 COUT 12 UOUT 13 VOUT 14 SDTO2 15 BICK2 16 LRCK2 17 SDTO1 18 BICK1 19 LRCK1 20 CDTO MS0339-E-00 80pin LQFP(0.5mm pitch) (Top View) ...
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... Frequency Response 80kHz Output pin #35,#37, #39,#41,#43,#45,#47,#49 Power Supply voltage Min=4.5V, Max=5.5V (*) The AK4589 has two register maps including ADC/DAC part (compatible with the AK4588) and DIR/DIT part (compatible with AK4588). Each register is selected by Chip Address. MS0339-E-00 AK4589 Differentianl 94dB 114dB Typ ± ...
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... DAC4 Audio Serial Data Input Pin 26 SDTI3 I DAC3 Audio Serial Data Input Pin 27 SDTI2 I DAC2 Audio Serial Data Input Pin 28 SDTI1 I DAC1 Audio Serial Data Input Pin 29 XTL1 I X’tal Frequency Select 0 Pin 30 XTL0 I X’tal Frequency Select 1 Pin MS0339-E-00 PIN/FUNCTION Function - 6 - [AK4589] 2004/09 ...
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... Power-Down Mode Pin 31 PDN I When “L”, the AK4589 is powered-down, all digital output pins go “L”, all registers are reset. When CAD1/0 pins are changed, the AK4589 should be reset by PDN pin. Master Mode Select Pin 32 MASTER I “H”: Master mode, “L”: Slave mode Zero Input Detect 2 Pin When the input data of the group 1 follow total 8192 LRCK cycles with “ ...
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... Master Clock Input Pin Transmit Channel (Through Data) Output 0 Pin Transmit Channel Output1 pin When DIT bit = “0”, Through Data. When DIT bit = “1”, DAUX2 Data. Interrupt 0 Pin PVDD 20k(typ) 20k(typ) PVSS VCOM Internal biased pin Circuit - 8 - [AK4589] 2004/09 ...
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... RX0-7, LOUT1-4, ROUT1-4, LIN, RIN INT0-1, BOUT, XTO, MCKO1-2, COUT, UOUT, VOUT, SDTO1-2, CDTO, DZF1-2, TX1-0 Digital CSN, DAUX1-2, SDTI1-4, XTL0-1 TEST1-3 MS0339-E-00 Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be connected to PVSS [AK4589] 2004/09 ...
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... AVDD -0.3 DVDD -0.3 PVDD -0.3 TVDD -0.3 ∆GND1 (Note 2) - ∆GND2 (Note 2) - IIN - VINA -0.3 VIND1 -0.3 VIND2 -0.3 VIND3 -0.3 Ta -10 Tstg -65 Symbol min AVDD 4.75 DVDD 4.75 PVDD 4.75 TVDD 2 [AK4589] max Units 6.0 V 6.0 V 6.0 V 6.0 V 0.3 V 0.3 V ±10 mA AVDD+0.3 V DVDD+0.3 V TVDD+0.3 V PVDD+0.3 V °C 70 °C 150 typ max Units 5.0 5.25 V 5.0 AVDD V 5.0 AVDD V 5 ...
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... ANALOG CHARACTERISTICS min 2. (Note 104 98 104 - 104 98 104 - - 90 ±2.5 (Note 6) 2 (Note 7) (Note 9) (Note 10) (Note 11 [AK4589] typ max Units 24 Bits 102 102 dB 102 102 dB 110 dB 0.2 0 ppm/°C 3.10 3.30 Vpp 25 kΩ 16 kΩ ...
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... -0.2dB - -3.0dB SB 28 (Note 13) GD ∆GD -3dB FR -0.1dB -0.1dB PB 0 -6.0dB - SB 26 (Note 13 (Note 14 (Note 14 [AK4589] typ max Units 18.9 kHz 20.0 - kHz 23.0 - kHz kHz ±0. 1/fs 0 µs 1.0 Hz 6.5 Hz 21.8 kHz 24.0 - kHz kHz ±0. 19.2 1/fs ±0.2 dB ± ...
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... VIL - (Table 15) VAC 40%DVDD VOH TVDD-0.4 VOH DVDD-0.4 VOH AVDD-0.4 (Iout=400µA) VOL - Iin - Symbol min Zin VTH 200 VHY - fs 32 PVDD 20k(typ) 20k(typ) VCOM PVSS Internal biased pin Circuit - 13 - [AK4589] typ max Units - - 0 30%DVDD Vpp - - 0.4 V ±10 µA ...
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... PDN “↑” to SDTO1 valid (Note 18) Notes: 2 16. “L” time format. 17. The AK4589 can be reset by bringing PDN “L” to “H” upon power-up. 18. These cycles are the number of LRCK rising from PDN rising. MS0339-E-00 =20pF) L Symbol min ...
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... Units ...
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... Clock Timing (TDM 256 mode, TDM 128 mode) MS0339-E-00 1/fCLK tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq tBCK tBCKH tBCKL Clock Timing (Normal mode) 1/fCLK tCLKH tCLKL 1/fs tLRH tLRL tBCK tBCKH tBCKL - 16 - [AK4589] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2004/09 ...
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... LRCK1 tBLR BICK1 SDTO1 SDTI Audio Interface Timing (TDM 256 mode, TDM 128 mode) MS0339-E-00 tLRB tSDS tSDH Audio Interface Timing (Normal mode) tLRB tSDS tSDH - 17 - [AK4589] VIH VIL VIH VIL tBSD 50%TVDD VIH VIL VIH VIL VIH VIL tBSD 50%TVDD ...
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... ASAHI KASEI LRCK1 tMBLR BICK1 SDTO1 DAUX1 MS0339-E-00 tDXS tDXH Audio Interface timing (Master Mode [AK4589] 50%TVDD 50%TVDD tBSD 50%TVDD VIH VIL 2004/09 ...
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... Units 24.576 MHz 24.576 MHz 24.576 MHz 24.576 MHz 192 kHz 192 kHz ...
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... Serial Interface Timing (Slave Mode [AK4589] VIH VIL = tECLKL x fECLK x 100 50%TVDD = tMCKL1 x fMCK1 x 100 50%TVDD = tMCKL2 x fMCK2 x 100 VIH VIL = tLRL 100 VIH VIL tBCKH ...
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... ASAHI KASEI LRCK2 tMBLR BICK2 SDTO2 DAUX2 PDN MS0339-E-00 tDXS tDXH Serial Interface Timing (Master Mode) tPW Power Down & Reset Timing - 21 - [AK4589] 50%TVDD 50%TVDD tBSD 50%TVDD VIH VIL VIL 2004/09 ...
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... components conveys a license under the Philips 2 C system, provided the system conform to the [AK4589] typ max Units 100 kHz µs - µs - µs - µs - µ ...
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... The ADC/DAC part doesn’t support READ command.. MS0339-E-00 tCSS tCCK tCCKL tCCKH tCDH tCDS C1 C0 R/W Hi-Z tCSW tCSH Hi-Z A0 tDCD [AK4589] VIH VIL VIH VIL VIH A4 VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%TVDD D5 2004/09 ...
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... The ADC/DAC part doesn’t support READ command. tPD PDN SDTO MS0339-E-00 tCSW tCSH tHIGH tF tSU:DAT tSU:STA Start Bus mode Timing tPDV Power-down & Reset Timing - 24 - [AK4589] VIH VIL VIH VIL VIH VIL tCCZ 50%TVDD VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL 50%TVDD 2004/09 ...
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... In slave mode, external clocks (MCLK, BICK1, LRCK1) should always be present whenever the AK4589 is in normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4589 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4589 should be in the power-down mode (PDN pin = “ ...
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... Table 7. System Clock Example (Auto Setting Mode) De-emphasis Filter The AK4589 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 bits (DAC1: DEMA1-0 bits, DAC2: DEMB1-0 bits, DAC3: DEMC1-0 bits, DAC4: DEMD1-0 bits, see “ ...
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... M J 24bit 24bit 24bit 24bit 24bit [AK4589] LRCK1 pin BICK1 pin Input Input “L” output “L” output Input Input “L” output “L” output Input Input Output Output LRCK1 ...
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... 24bit 24bit 24bit 20bit 24bit 24bit 24bit 24bit 24bit 24bit [AK4589] LRCK1 BICK1 I/O I/O ↑ I 256fs I ↑ I 256fs I ↑ I 256fs I 2 ↓ 256fs I ↑ O 256fs O ↑ ...
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... Don’t Care 23 22 Figure 3.Mode 2,6 Timing Don’t Care 23 22 Lch Data Figure 4. Mode 3 ,7 Timing - 29 - [AK4589 Rch Data ...
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... B ICK 23 0 Rch 32 B ICK ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK Figure 8. Mode 11 ,15 Timing - 30 - [AK4589 ICK 32 B ICK ...
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... Rch 32 B ICK ICK 32 B ICK ICK 32 B ICK Figure 11. Mode 18 ,22 Timing - 31 - [AK4589 ICK BICK ICK 0 23 ...
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... B ICK MS0339-E-00 128 B ICK Rch 32 B ICK ICK 32 B ICK ICK 32 B ICK Figure 12. Mode 19 ,23 Timing - 32 - [AK4589 ICK BICK 2004/09 ...
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... ASAHI KASEI Overflow Detection The AK4589 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 16/fs = 333µs @fs=48kHz). OVF pin is “L” for 522/fs (=11.8ms @fs=48kHz) after PDN = “ ...
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... ASAHI KASEI Digital Attenuator The AK4589 has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 15). ATT7-0 Table 15. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 16). Transition between set values is the soft transition ...
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... DZF “H”. System Reset The AK4589 should be reset once by bringing PDN pin = “L” upon power-up. The AK4589 is powered up and the internal timing starts clocking by LRCK1 “↑” after exiting reset and power down state by MCLK. The AK4589 is in the power-down mode until MCLK and LRCK1 are input ...
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... Power ON/OFF Sequence The ADC and DACs of AK4589 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “ ...
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... There is a delay, 4~5/fs from RSTN1 bit “0” to the internal RSTN bit “0”. MS0339-E-00 4~5/fs (9) 1~2/fs (9) (1) 516/fs Digital Block Power-down Init Cycle Digital Block Power-down Normal Operation (2) GD (3) “0”data “0”data (2) GD (6) (5) (6) (7) Don’t care 4∼5/fs (8) Figure 15. Reset sequence example - 37 - [AK4589] Normal Operation GD (4) GD 2004/09 ...
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... ASAHI KASEI DAC partial Power-Down Function All DACs of The AK4589 can be powered-down individually by PD1-4 bits. The analog part of DAC is in power-down by PD1-4 bits =”1”, however, the digital part is not in power-down by it. Even if all DACs were set in power-down by the partial power-down bits, the digital part continue to function. The analog output of the channel which is set in power-down by PD1-4 bits is fixed to the voltage of VCOM ...
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... TDM1 TDM0 SDTI Sampling Speed 0 1-4 Normal, Double, Four Times Speed 1 1 Normal Speed 1 1-2 Double Speed - 39 - [AK4589 DIF1 DIF0 0 SMUTE SDOS DFS0 ACKS CKS0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...
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... In the case of PWADN bit =”0” and PWDAN bit =”0”, the setting of LOOP1-0 bits become invalid. And ADC is selected. And it becomes the normal operation (No loop back). MS0339-E- CKS1 DFS1 LOOP1 LOOP0 [AK4589 SDOS DFS0 ACKS CKS0 2004/09 ...
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... ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 DEMD DEMA DEMA [AK4589 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ...
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... Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0339-E- PD4 ATS1 ATS0 DZFM3 DZFM2 DZFM1 DZFM0 [AK4589 PD3 PD2 PD1 RSTN1 PWVRN PWADN PWDAN 2004/09 ...
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... AK4589 detects the stream again. 192kHz Clock Recovery On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4589 has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel status, AK4589 detects the sampling frequency (32kHz, 44 ...
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... ASAHI KASEI Clock Source The following circuits are available to feed the clock to XTI pin of AK4589. 1) X’tal XTI C C XTO Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock - Note: Input clock must not exceed DVDD. XTI External Clock 25kΩ ...
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... ASAHI KASEI Sampling Frequency and Pre-emphasis Detection The AK4589 has two methods for detecting the sampling frequency as follows. 1. Clock comparison between recovered clock and X’tal oscillator 2. Sampling frequency information on channel status Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits. ...
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... Table 24. De-emphasis Manual Control at DEAU bit = “0” System Reset and Power-Down The AK4589 has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4589 should be reset once by bringing PDN pin = “ ...
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... IPS1 IPS0 INPUT Data Table 25. Recovery Data Select 1/4fs C(L0) C(R0) C(L1) L0 L191 R191 Figure 21 output/input timings - 47 - [AK4589] RX0 Default RX1 RX2 RX3 RX4 RX5 RX6 RX7 C(L39) C(R39) C(L40) L39 L38 R38 2004/09 ...
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... CT39-CT0 bits in control registers. When bit0= “0”(consumer mode), bit20-23 (Audio channel) could not be controlled directly but be controlled by CT20 bit. When the CT20 bit is “1”, AK4589 outputs “1000” as C20-23 for left channel and output “0100” at C20-23 for right channel automatically. When CT20 bit is “0”, AK4589 outputs “0000” ...
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... For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is available and RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”. The AK4589 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure transformer of 1:1. ...
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... ASAHI KASEI Q-subcode buffers The AK4589 has Q-subcode buffer for CD application. The AK4589 takes Q-subcode into registers by following conditions. 1. The sync word (S0,S1) is constructed at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit. 4. The distance between two start bits are 8-16 bits. ...
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... Each INT0/1 pins can mask those eight events individually. Once PAR, QINT and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4589 loses lock, registers regarding C-bit or U-bits are not initialized and keep previous value ...
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... SDTO2 (UNLOCK) SDTO2 (PAR error) SDTO2 (others) VOUT pin (UNLOCK) VOUT pin (except UNLOCK) MS0339-E-00 (Error) Hold ”1” Free Run (fs: around 20kHz) Previous Data Figure 29. INT0/1 pin timing - 52 - [AK4589] Hold Time (max: 4096/fs) Hold Time = 0 Reset READ 06H Normal Operation 2004/09 ...
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... Muting Figure 30. Error Handling Sequence Example 1 MS0339-E-00 PDN pin ="L" to "H" Initialize Read 06H INT0/1 pin ="H" No Yes Mute DA C output Read 06H (Each Error Handling) Read 06H (Res ets registers) No INT0/1 pin ="H" Yes - 53 - [AK4589] 2004/09 ...
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... MS0339-E-00 PDN pin ="L" to "H" Initialize Read 06H INT1 pin ="H" No Yes Read 06H and Detect QSUB= “1” (Read Q-buffer) No New data QCRC = “0” Yes No INT1 pin ="L" Yes New data is valid - 54 - [AK4589] is invalid 2004/09 ...
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... When using Master mode, BICK2 and KRCK2 output pins are Hi-Z during PDN pin = “L” and from PDN pin = “H” to entering Master mode. When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4589 continues to output the last normal sub-frame data from SDTO2 repeatedly until the error is removed. When the Unlock Error occurs, AK4589 output “ ...
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... Lch Data Mode4 : LRCK2, BICK2 : Output Mode6 : LRCK2, BICK2 : Input Lch Data Mode5 : LRCK2, BICK2 : Output Mode7 : LRCK2, BICK2 : Input - 56 - [AK4589 Rch Data ...
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... Q38 Q49 Q48 Q47 Q46 Q57 Q56 Q55 Q54 Q65 Q64 Q63 Q62 Q73 Q72 Q71 Q70 Q81 Q80 Q79 Q78 - 57 - [AK4589 OCKS1 OCKS0 PWN RSTN2 DEAU DEM1 DEM0 DFS TX0E OPS02 OPS01 OPS00 DIT IPS2 IPS1 IPS0 MPE0 ...
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... DIF2-0: Audio Data Format Control (see Table 29.) MS0339-E- CS12 BCU CM1 CM0 R/W R/W R/W R DIF2 DIF1 DIF0 RD R/W R/W R [AK4589 OCKS1 OCKS0 PWN RSTN2 R/W R/W R/W R DEAU DEM1 DEM0 DFS R/W R/W R/W R 2004/09 ...
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... OPS12 OPS11 OPS10 TX0E R/W R/W R/W R EFH1 EFH0 UDIT 0 R/W R/W R Recovered U bit is used for DIT (loop mode for U bit) 01: 1024 LRCK2 11: 4096 LRCK2 - 59 - [AK4589 OPS02 OPS01 OPS00 R/W R/W R/W R DIT IPS2 IPS1 IPS0 R/W R/W R/W R ...
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... MQI1: Mask Enable for QINT bit 0: Mask disable 1: Mask enable MS0339-E- MQI0 MAT0 MCI0 MUL0 R/W R/W R/W R MQI1 MAT1 MCI1 MUL1 R/W R/W R/W R [AK4589 MDTS0 MPE0 MAN0 MPR0 R/W R/W R/W R MDTS1 MPE1 MAN1 MPR1 R/W R/W R/W R 2004/09 ...
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... Non Audio Detect 1: Out of Lock 1: Changed 1: Detect 1: Changed FS3 FS2 FS1 FS0 1:Error 1:Error 1:Invalid - 61 - [AK4589 PEM AUDION PAR QCRC CCRC ...
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... D5 D4 PC7 PC6 PC5 PC4 PC15 PC14 PC13 PC12 PC11 PD7 PD6 PD5 PD4 PD15 PD14 PD13 PD12 PD11 RD Not initialized - 62 - [AK4589 CR3 CR2 CR1 CR0 CR10 CR9 CR8 CR18 CR17 CR16 CR26 CR25 CR24 CR34 CR33 CR32 D3 D2 ...
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... Q56 Q55 Q54 Q53 Q65 Q64 Q63 Q62 Q61 Q73 Q72 Q71 Q70 Q69 Q81 Q80 Q79 Q78 Q77 RD Not initialized - 63 - [AK4589 Q12 Q11 Q10 Q20 Q19 Q18 Q28 Q27 Q26 Q36 Q35 Q34 Q44 Q43 Q42 Q52 ...
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... LSB 16 bits of bitstream 0 Burst_payload repetition time of the burst Figure 37. Data structure in IEC60958 Contents sync word 1 sync word 2 Burst info Length code Table 30. Burst preamble words - 64 - [AK4589 MSB stuffing Value 0xF872 0x4E1F see Table 31 Numbers of bits 2004/09 ...
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... MS0339-E-00 Table 31. Fields of burst info [AK4589] Repetition time of burst in IEC60958 frames ≤4096 1536 384 1152 1152 1024 384 1152 512 ...
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... MS0339-E- Repetition time >4096 frames Figure 38. Timing example 1 <20mS (Lock time) Stop 2~3 Syncs (B Figure 39. Timing example [AK4589 INT0 hold time <Repetition time Pc ...
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... CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4589 should be reset by PDN pin = “L”. Register of ADC/DAC part can not read. CSN ...
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... All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4589 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE) ...
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... In the read mode, the slave, the AK4589 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data ...
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... The AK4589 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4589 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “ ...
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... Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4589 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter the master does ...
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... AVSS, DVSS and PVSS must be connected the same analog ground plane. - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4589 with low impedance on PC board. MS0339-E-00 ...
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... VREFH Vpp (typ). The ADC output data format is 2’s complement. The DC offset is removed by the internal HPF. The AK4589 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4589 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... AOUTL 330 3.9n 4 NJM5534D + 0.1u 680 3.3n + 100u 180 0. AOUTL 3.9n 330 4 NJM5534D + 0.1u 680 Figure 51. External 2nd order LPF Circuit Example MS0339-E-00 10u 10u 620 620 10u 10u - 74 - [AK4589] +15 -15 10u 0.1u + 560 1.0n 100 Lch + 3 7 1.0n NJM5534D + 10u 0.1u 2004/09 ...
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... ASAHI KASEI 80-pin LQFP ( Unit : 0.50 1.25TYP 0.50±0.1 Material & Lead finish Package: Epoxy Lead-frame: Copper Lead-finish Soldering (Pb free) plate MS0339-E-00 PACKAGE 14.0±0.2 12.0±0 0.20±0.1 0. [AK4589] 0° ~ 10° 2004/09 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0339-E-00 MARKING AK4589VQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4589VQ 4) Asahi Kasei Logo Revision History Page Contents IMPORTANT NOTICE - 76 - [AK4589] ...