ak4646 AKM Semiconductor, Inc., ak4646 Datasheet - Page 68
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ak4646
Manufacturer Part Number
ak4646
Description
Stereo Codec With Mic/spk-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
1.AK4646.pdf
(79 pages)
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MS0557-E-02
Power Supply
Internal Clock
PMVCM bit
(Addr:00H, D6)
(Addr:01H, D0)
2. PLL Slave Mode (LRCK or BICK pin)
PMPLL bit
<Example>
LRCK pin
BICK pin
PDN pin
(1) After Power Up: PDN pin “L”
(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
(5) Normal operation stats after that the PLL is locked.
supplied. PLL lock time is 160ms (max) when LRCK is a PLL reference clock. And PLL lock time is 2ms (max)
when BICK is a PLL reference clock.
“L” time of 150ns or more is needed to reset the AK4646.
VCOM should first be powered up before the other block operates.
(1)
(2)
(3)
Figure 39. Clock Set Up Sequence (2)
“H”
Input
(4)
“1”
- 68 -
(5)
4fs of
(1) Power Supply & PDN pin = “L”
Example:
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(2) Addr:04H, Data:32H
(3) Addr:00H, Data:40H
(4) Addr:01H, Data:01H
Addr:05H, Data:27H
[AK4646]
“H”
2007/05