ak4642e AKM Semiconductor, Inc., ak4642e Datasheet - Page 17

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ak4642e

Manufacturer Part Number
ak4642e
Description
Stereo Codec With Mic/hp/spk-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
Parameter
Control Interface Timing (3-wire Serial mode)
Control Interface Timing (I
Power-down & Reset Timing
Note 35. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 36. The AK4642 can be reset by the PDN pin = “L”.
Note 37. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
MS0420-E-00
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 35)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
CCLK Period
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
PDN Pulse Width
PMADL or PMADR “↑” to SDTO valid (Note 37)
Pulse Width High
2
C Bus mode):
(Note 36)
- 17 -
tHD:DAT
tHD:STA
tSU:DAT
tSU:STA
tSU:STO
Symbol
tCCKH
tCCKL
tHIGH
tLOW
tCSW
tCCK
tCDH
tCDS
tCSH
tBUF
tPDV
fSCL
tCSS
tPD
tSP
tR
tF
min
200
150
150
1.3
0.6
1.3
0.6
0.6
0.1
0.6
80
80
40
40
50
50
0
0
-
-
-
-
1059
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
400
0.3
0.3
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
[AK4642EN]
Units
2005/09
kHz
1/fs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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