ak4626a AKM Semiconductor, Inc., ak4626a Datasheet - Page 28
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ak4626a
Manufacturer Part Number
ak4626a
Description
High Performance Multi-channel Audio Codec
Manufacturer
AKM Semiconductor, Inc.
Datasheet
1.AK4626A.pdf
(40 pages)
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ASAHI KASEI
The AK4626A can control its functions via registers. Internal registers may be written by 2 types of control mode. The
chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4626A should be reset by PDN pin.
MS0397-E-00
Serial Control Interface
(1) 3-wire Serial Control Mode (I2C = “L”)
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max).
* Writing to control register is invalid when PDN = “L”.
* AK4626A does not support the read command.
Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
CCLK
CSN
CDTI
C1
0
C0
1
R/W
Figure 16. 3-wire Serial Control I/F Timing
2
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W:
A4-A0: Register Address
D7-D0: Control Data
A4
3
A3
4
Read/Write (Fixed to “1”, Write only)
A2
5
A1
6
- 28 -
A0
7
D7
8
D6
9
D5
10 11 12 13 14 15
D4
D3
D2
D1
D0
[AK4626A]
2005/06