ak7712a-vt AKM Semiconductor, Inc., ak7712a-vt Datasheet - Page 17

• Manufacturer Part Number: ak7712a-vt
• Description: Built-in 20-bit Adc/dac Sophisticated Audio Dsp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
1) Audio Interface Timing
2) Microcomputer Interface Timing
0180-E-02
note 1 : This standard value is provided for not to be overlapped the edge of LRCK and BCLK" " each other.
note 1 : Master clock cycle × 3
note 2 : See timing chart.
(AVDD=DVDD,AVB,DVB=5.0V±5%,Ta=25 C;
(AVDD=DVDD,AVB,DVB=5.0V±5%,Ta=25 C;
Slave mode
Master mode
Master clock 16.9344MHz,XTI=384fs[fs=44.1kHz]; CL=20pF)
BCLK cycle
BCLK pulse width Low
Time from BCLK" " to LRCK (note 1)
Delay time from LRCK to DOUT(MSB)
Delay time from BCLK" " to DOUT
Latch hold time of SDIN
Latch setup time of SDIN
BCLK cycle
Duty cycle
BCLK pulse width Low
Time from BCLK" " to LRCK
Delay time from LRCK to DOUT(MSB)
Delay time from BCLK" " to DOUT
Latch hold time of SDIN
Latch set Up time of SDIN
From CS" " to WRQ" "
From RST" " to WRQ" "
From WRQ" " to CS" "
From WRQ" " to RST" "
From WRQ" " to SCLK" "
From Last SCLK" " to WRQ" "
SCLK cycle
SCLK pulse width Low
SI latch hold time
SI latch set Up time
From CS" " to
From CS" " to SO,WRDY"Hi-z"
From CS" " to DRDY" "
From SCLK" " to SO setup time
master clock 16.9344MHz,XTI=384fs[fs=44.1kHz];CL=20pF)
cancellation of SO,WRDY "Hi-z" (note2)
pulse width High
pulse width High
pulse width High
Parameter
Parameter
(note2)
(note2)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Symbol
CSW
RSW
WRC
WRS
WSC
SCW
SLK
SLKL
SLKH
SIH
SIS
CSHR
CSHS
CSDR
SOS
- 17 -
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BLK
BLKL
BLKH
BLR
LRD
BLKD
DINH
DINS
BLK
BLKL
BLKH
BLR
LRD
BLKD
DINH
DINS
166(note1)
312.5
100.0
100.0
30-t
40
40
100.0
100.0
-20
40
40
100
100
100
100
100
200
min
min
80
80
50
50
BLKH
64fs
50
typ
typ
30+t
70
70
20
70
70
max
max
100
800
100
BLKL
[AK7712A-VT]
40
1997/12
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns