ak4140 AKM Semiconductor, Inc., ak4140 Datasheet - Page 8

• Manufacturer Part Number: ak4140
• Description: Digital Btsc Decoder
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
Parameter
Audio Interface Timing (Master mode)
Power-Down & Reset Timing
Note 6. SCLK rising edge must not occur at the same time as LRCK edge.
Note 7. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 8. The AK4140 can be reset by bringing the PDN pin = “L”.
Note 9. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Note 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS0547-E-01
Parameter
Control Interface Timing (I
PDN Pulse Width
PDN “↑” to SDTO valid
Normal mode (TDM1=“L”, TDM0=“L”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDM256 mode (TDM1=“L”, TDM0=“H”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
TDM128 mode (TDM1=“H”, TDM0=“H”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 10)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Capacitive load on bus
Suppressed by Input Filter
(prior to first clock pulse)
2
C Bus):
(Note 8)
(Note 7)
(Note 9)
Symbol
tMBLR
tMBLR
tMBLR
dBCK
dBCK
dBCK
fBCK
fBCK
fBCK
tPDV
tBSD
tBSD
tSDH
tBSD
tSDH
tSDS
tSDS
tPD
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
- 8 -
Symbol
min
−20
−40
−12
−20
−12
−20
150
10
10
10
10
Min
1.3
0.6
1.3
0.6
0.6
0.1
0.6
0
0
0
-
-
-
256fs
128fs
64fs
516
typ
50
50
50
typ
max
max
400
400
20
40
12
20
12
20
0.3
0.3
50
-
-
-
-
-
-
-
-
[AK4140]
Units
Units
kHz
2007/03
1/fs
pF
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
Hz
Hz
Hz
%
ns
ns
%
ns
ns
ns
ns
%
ns
ns
ns
ns
ns