atr2732n1 ATMEL Corporation, atr2732n1 Datasheet - Page 9

• Manufacturer Part Number: atr2732n1
• Description: Integrated Dab One-chip Front End
• Manufacturer: ATMEL Corporation

3.14
3.14.1
Figure 3-2.
9130AS–DAB–04/08
MOSI
MOSI
MISO
SCK
SCK
NSS
NSS
SPI Bus
Programming via SPI
t
cet
Timing Diagram of the SPI Interface (16 Bits per Transfer)
MSB
MSB
t
A3
sud
t
hda
A2
Adress
t
ch
t
per
The bus interface can be adapted to the signal voltage as a result of the supply voltage of the
external baseband processing unit connected to the bus. This is done with the help of a sensing
pin, VDI, which checks the supply voltage of the processor. The interface adapts itself to any
voltage between 1.65V and 3.5V.
Some things need to be taken into account when programming the ATR2732N1 via the SPI
interface: the data packet needs to be properly configured to write into the 14 different registers.
There are 16 registers. Fourteen of them are used to control the ATR2732N1. The two others,
registers 15 and 16, are Test Mode Registers. All these registers need to be reset by writing “0”
to every bit of each register one time, before starting the configuration of the ATR2732N1.
There are 4 address bits (bit 12 is address bit 0; bit 15 is address bit 3) which are used to select
the correct register. These are followed by 12 data bits (LSB is bit 0; MSB is bit 11). There is a
definite transmit order which needs to be considered: the MSB must be transmitted first (bit 15,
address bit 3), and LSB (data bit 0) last.
Unused and test mode register bits may not be documented in the datasheet and have to be set
to “0” in customer applications. Information about the status of the device is available by reading
one word (16 bits) out of the part.
Note:
t
cl
A1
A0
It is absolutely necessary to set the NSS signal back to high after every SPI access.
D11
t
t
t
t
t
t
cet
sud
hda
per
ch
cl
:
:
:
:
:
:
Clock period
Clock high time
Data setup time
Hold time of MOSI
Clock low time
Clock enable time
D10
D9
D8
D7
D6
Data
D5
D4
D3
D2
ATR2732N1
D1
LSB
LSB
D0
*
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