ispgal22v10av Lattice Semiconductor Corp., ispgal22v10av Datasheet - Page 4

• Manufacturer Part Number: ispgal22v10av
• Description: In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic ?
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 5. Logic Diagram/JEDEC Fuse Map – PLCC & (QFN) Package Pinout
JEDEC Fuse #131
13 (10)
10 (7)
11 (8)
2 (30)
3 (31)
4 (32)
12 (9)
Fuse #0
5 (1)
6 (2)
7 (3)
9 (6)
JEDEC
0
4
8
12
S1, S0 = Arch Control Bits
SR = Slew Rate Bit
OD = Open Drain Bit
16
20
24
28
32
4
36
40
ispGAL22V10AV/B/C Data Sheet
JEDEC Fuse #5807
16
12
10
14
16
14
10
12
8
8
S1, S0 = 5808, 5809
S1, S0 = 5810, 5811
S1, S0 = 5812, 5813
S1, S0 = 5814, 5815
S1, S0 = 5816, 5817
S1, S0 = 5818, 5819
S1, S0 = 5820, 5821
S1, S0 = 5822, 5823
S1, S0 = 5824, 5825
S1, S0 = 5826, 5827
JEDEC
Fuse #5676
SR = 5830
OD = 5831
SR = 5832
OD = 5833
SR = 5834
OD = 5835
SR = 5836
OD = 5837
SR = 5838
OD = 5839
SR = 5840
OD = 5841
SR = 5842
OD = 5843
SR = 5844
OD = 5845
SR = 5846
OD = 5847
SR = 5848
OD = 5849
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
16 (14)
27 (26)
26 (25)
25 (24)
24 (23)
23 (22)
21 (19)
20 (18)
19 (17)
18 (16)
17 (15)