ispgal22v10av Lattice Semiconductor Corp., ispgal22v10av Datasheet - Page 5

• Manufacturer Part Number: ispgal22v10av
• Description: In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic ?
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Electronic Signature
An electronic signature (ES) is provided in every ispGAL22V10A device. It contains 32 bits of reprogrammable
memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory con-
trol. The signature data is always available to the user independent of the state of the security cell. IEEE 1149.1
and IEEE 1532 compliant USERCODE is supported.
Low Power and Power Management
The ispGAL22V10A family is designed with high speed low power design techniques to offer both high speed and
low power. With an advanced E
ispGAL22V10A family offers fast pin-to-pin speeds, while simultaneously delivering low standby power without
requiring any “turbo bits” or other traditional power-management schemes.
I/O Configuration
Each output supports a variety of output standards dependent on the V
open drain operation. Each input can be programmed to support a variety of standards, independent of the V
supplied to its I/O. For 28 PLCC package the V
pendent of V
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each ispGAL22V10A device I/O has an individually programmable output slew rate control bit. Each output can be
individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set-
ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflec-
tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the
fast slew rate can be used to achieve the highest speed.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispGAL22V10A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
interface that corresponds to the power supply voltage.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. All ispGAL22V10A devices provide In-Sys-
tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE
1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well-
defined interface. All ispGAL22V10A devices are also compliant with the IEEE 1532 standard.
The ispGAL22V10A devices can be programmed across the commercial temperature and voltage range. The PC-
based Lattice software facilitates in-system programming of ispGAL22V10A devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
• LVTTL
• LVCMOS 3.3
• LVCMOS 2.5
CC
is available with the 32 QFN package only. The I/O standards supported are:
• LVCMOS 1.8
• 3.3V PCI Compatible
2
low power cell and no sense-amplifiers (full CMOS logic approach), the
CCO
and V
5
CC
must be the same. The option to set the V
ispGAL22V10AV/B/C Data Sheet
CCO
. Outputs can also be configured for
CCO
inde-
CCO