msm7581 Oki Semiconductor, msm7581 Datasheet
msm7581
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msm7581 Summary of contents
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... MSM7581 ITU-T G.721 4ch ADPCM TRANSCODER GENERAL DESCRIPTION The MSM7581 is an ADPCM transcoder which is used by the new digital cordless system. It converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice versa. This device is consists of four systems with full-duplex voice data channels and a data-through mode ...
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... DECODER MUTE PLL MCK CODER PAD/ DECODER MUTE PLL MCK CODER PAD/ DECODER MUTE PLL MCK CODER PAD/ DECODER MUTE MSM7581 PLCKEN THR1 PLCK1 SYXA1 BCKA1 CODER SOA1 P S SIA1 "0000" DECODER DETECT P S DET1 SYRA1 PDN1 THR2 PLCK2 SYXA2 BCKA2 ...
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... NC 11 PDN1 PDN2 BCKA2 16 SYRA2 17 DET2 SIA2 20 SOA2 21 SYXA2 22 PLCK2 23 THR2 connect pin 100-Pin Plastic TQFP MSM7581 75 NC THR4 74 73 PLCK4 72 SYXA4 SOA4 71 SIA4 DET4 68 SYRA4 67 66 BCKA4 NC 65 PDN4 PDN3 BCKA3 60 59 ...
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... The PCM output can be attenuated and set to an out-of-service pattern (idle pattern) by controlling these pins. Set these pins to digital "0" level during normal operation.The control sequences are as follows: PAD11 - PAD41 PAD10 - PAD40 MSM7581 Normal 6 dB Loss 12 dB Loss Out-of-service Pattern 4/18 ...
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... PCM data companding law selection. Digital “1” and “0” correspond to A-law and -law, respectively. PDN1, PDN2, PDN3, PDN4 Power down mode selection. PDN1 - 4 can be independently set to power down mode. When digital “0” is applied, these pins are in the power-down mode. MSM7581 5/18 ...
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... A digital "1" is output at the rising edge of the clock. The fourth data bit (LSB) is clocked into the register by the bit clock (BCKA and held there until the rising edge in the next time frame. When detecting the special data pattern in the next time frame, the digital "1" on the pins DET ( remains. MSM7581 6/18 ...
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... Set this pin at digital "0" during normal operation since it is used as the control pin for testing the IC. PLCK1 - 4 Output pins of the 8 kHz clock from PLLs. When PLCKEN = "1", the 8 kHz clock pulses synchronized with external signals are applied to SYXA1 - 4 outputs. When PLCKEN = "0", "0" level is output to these pins. MSM7581 7/18 ...
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... All Digital Input Pins BCKP1 - 4 to SYXP1 - 4 SYXA1 - 4 to BCKA1 - 4 BCKA1 - 4 to SYRA1 - 4 SYRP1 - 4 to BCKP1 - 4 SYXP1 - 4, SYRP1 - 4 SYXA1 - 4, SYRA1 - 4 — — SOP1 - 4, SOA1 - 4 (Pull-up Resistor) SOP1 - 4, SOA1 - 4 DET1 - 4, PLCK1 - 4 MSM7581 Rating Unit –0 0 –55 to +150 °C Min. Typ. ...
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... DET1 - 4, PLCK1 - –0.4 mA 0.5 ¥ SOA1 - 4, SOP1 - 4, Pull-up ≥ 500 W DET1 - 4, PLCK1 - SOP1 - 4, SOA1 - 4 All Digital Input Pins (V DD Condition 1 LSTTL + 100 pF Pull-up: 500 W MSM7581 = 2 5 –30°C to +80°C) Typ. Max. Unit — — — ...
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... DD1 Note: 4 bit data pattern except "0000" XD2 t XD3 LSB LSB RD2 "0000" MSM7581 LSB RD3 LSB Note) t DD2 10/18 ...
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... The PAD pin must be controlled cover these processings. The PAD signal is input in the device at the rising edge of SYXP. Therefore, the PAD signal should be input at ts and th for the rise of SYXP. 78.125ms 78.125ms LSB PAD processing transmit data MSM7581 0dB transmit data 11/18 ...
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... Through-data Output (SOA) BCKA THR Note: That data-ship may occur when the rising edge (data load point) of SYXA and input of the internal latch timing overlap each other. Through-data 8b ADPCM Latch CODER LSB MSM7581 SYNCA Parallel S E SOA L Serial BCLKA 4b Through-data MSB ...
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... PCM side SYNC (SYXP) Throgh-data output (SOP) BCLKP THR Less than are BCLKP cycle from the rising edge of SYXA signal. Through-data 8b ADPCM Latch DECODER Latch timing=A LSB MSM7581 SYNCP Parallel S E SOP L Serial BCLKP 8b Through-data This data is output here. MSB 100ns or more ...
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... SYXP2 BCKP2 30 SOP2 29 SIP2 28 SYRP2 27 RES2 MSM7581 8 kHz Synchronous Signal (Channel CODER 3 Side PCM Intput DECODER 3 Side PCM Output DECODER 2 Side PCM Output CODER 2 Side PCM Intput 8 kHz Synchronous Signal (Channel 2) Shift Clock (Channel ...
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... The data slip means that data is deleted or the same data is output twice PCMDATA2 ADPCMDATA1 ADPCMDATA0 *t1 is the falling edge of the 8th BCLK counted from t0 ADPCMDATA2 PCMDATA1 PCMDATA0 *t1 is the falling edge of the 8th BCLK counted from t0. MSM7581 PCMDATA3 ADPCMDATA2 ADPCMDATA1 ADPCMDATA3 PCMDATA2 PCMDATA1 15/18 ...
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... Latch Latch From To DECODER DECODER SYXA MSM7581 * t4 is the falling edge of the 8th BCLK counted from the rising edge of SYXP the rising edge of SYXA the falling edge of the 4th BCLK MSB counted from the rising edge of SYRA the rising edge of SYRP. ...
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... Therefore, the timings of SYNC signals of both PCM and ADPCM sides should not be set up in the range about 500nsec of Tsip=t1, Tsia=t3 and Tsop=t2. For normal operation, SYNC clocks for ADPCM and PCM sides should be continuous at 8 kHz and synchronized with each other even if their phases are different. MSM7581 17/18 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM7581 (Unit : mm) Package material Epoxy resin ...