msm7718-01 Oki Semiconductor, msm7718-01 Datasheet - Page 5

• Manufacturer Part Number: msm7718-01
• Description: Echo Canceler With Adpcm Codec
• Manufacturer: Oki Semiconductor

¡ Semiconductor
SGT, SGR
Outputs of the analog signal ground voltage.
SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the analog
signal ground voltage for the receive system. The output voltage is approximately 1.4 V. Connect
bypass capacitors of 10 mF and 0.1 mF (ceramic type) between these pins and the AG pin. However
to reduce the response time of the receiver power-on, it is recommended to apply bypass capacitors
of 1 mF and 0.1 mF. During power-down, the output changes to 0 V.
AG
Analog ground.
DG1, 2, 3
Digital ground.
V
+3 V power supply for analog circuits.
V
+3 V power supply for digital circuits.
PDN/RST
Power-down reset control input.
A logic “0” makes the LSI device enter a power-down state. At the same time, all control register
data is reset to the initial state. Set this pin to a logic “1” during normal operating mode. Since the PDN/
RST pin is ORed with CR0-B5 of the control register, set CR0-B5 to digital “0” when using this pin.
PDWN
Power-down control input.
When set to a logic “0”, the device changes to the power-down state, but each bit of control register
and internal variables of control register are retained. During normal operation, set this pin to logic
“1”. Since the PDWN pin is ORed with CR0-B6 of the control register, set CR0-B6 to logic “0” when
using this pin.
MCK
Master clock input.
The frequency must be 9.6 MHz or 19.2 MHz. The master clock signal is allowed to be asynchronous
with SYNCP, SYNCA, BCLKP, and BCLKA.
DDA
DDD1, 2, 3
MSM7718-01
5/38