msm7728 Oki Semiconductor, msm7728 Datasheet - Page 8

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msm7728

Manufacturer Part Number
msm7728
Description
Single Rail Linear Codec
Manufacturer
Oki Semiconductor
Datasheet
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Power Supply Voltage
Operating Temperature
Analog Input Voltage
High Level Input Voltage
Low Level Input Voltage
Clock Frequency
Sync Pulse Frequency
Clock Duty Ratio
Digital Input Rise Time
Digital Input Fall Time
Sync Signal Timing
High Level Sync Pulse Width *1
Low Level Sync Pulse Width *1
PCMIN Setup Time
PCMIN Hold Time
Digital Output Load
DCLK Pulse Width
WRN Timing
WRN Period
2048 kHz.
Parameter
Parameter
Symbol
Symbol
P
t
t
T
t
t
t
t
t
t
V
V
V
V
R
V
C
V
WSH
WCH
WR1
WR2
WR3
WR4
V
t
t
WSL
t
t
WCL
D
WRN
Ta
F
F
STG
t
t
DH
AIN
XS
SX
DS
AIN
DIN
DD
DD
DL
Ir
DL
IH
If
IL
C
S
C
Gain = 1
SYNC, BCLK, PCMIN, WRN,
RDN, DCLK, CDIN, RSTN
BCLK
SYNC
BCLK
SYNC, BCLK, PCMIN, WRN,
RDN, DCLK, CDIN, RSTN
BCLKÆSYNC, See Fig.1
SYNCÆBCLK, See Fig.1
SYNC, See Fig.1
SYNC, See Fig.1
Refer to Fig.1
Refer to Fig.1
Pull-up resistor
DCLK Low width, See Fig.2
DCLK High width, See Fig.2
DCLKÆWRNL, See Fig.2
WRNLÆDCLK, See Fig.2
DCLKÆWRNH, See Fig.2
WRNHÆDCLK, See Fig.2
AG = DG = 0 V
AG = DG = 0 V
AG = DG = 0 V
Condition
Condition
14 ¥ Fs
1 BCLK
1 BCLK
9DCLK
0.45 ¥
Min.
–30
V
100
100
100
100
2.5
4.0
0.5
40
50
50
50
50
50
50
0
DD
–0.3 to V
–0.3 to V
–0.3 to +7.0
–55 to +150
Rating
Typ.
+25
3.0
8.0
50
DD
DD
+ 0.3
+ 0.3
128 ¥ Fs
0.16 ¥
Max.
+85
V
V
100
3.6
1.4
12
60
50
50
DD
DD
MSM7728
Unit
Unit
8/23
V
kHz
kHz
kW
°C
°C
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
%
V
V
V
V
V
V
PP

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