msm7630 Oki Semiconductor, msm7630 Datasheet - Page 48
msm7630
Manufacturer Part Number
msm7630
Description
Universal Speech Processor
Manufacturer
Oki Semiconductor
Datasheet
1.MSM7630.pdf
(95 pages)
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3. Registers
This is a register group used for bus control.
3.1 BEA: Bus Error Address
This register provides the address at the time a bus error occurred.
3.2 BSR: Bus Status Register
This register provides bus status information.
• bit[18:17] XSP: Sleep (read/write)
• bit[16] CSP: CPU Sleep (read/write)
• bit[14:12] ST: Status (read-only)
• bit[11:8] PEB: Parity Error Byte (read-only)
• bit[6:4] BES: Bus Error Status (read-only)
bit
bit
When the STBY signal is "L", these bits either stop the clock without CPU intervention (XSP = 00)
or stop the clock after waiting for the CPU suspend process (XSP = 11).
This bit indicates whether the CPU core is operating or suspended. Writing "1" will stop the CPU
core’s clock.
These bits save the status signals when an access by the CPU core causes a bus error.
These bits provide the byte position when a parity error occurs.
These bits provide the source of a bus error.
These bits will be "000" after reset.
31
31
BES = 000
BES = 001
BES = 010
BES = 100
No error
BIU register privilege violation
Parity error
Invalid space access
19 18 17 16
XSP
C
S
P
BEA
15 14
0
ST
12
11
PEB
8
7 6
0
BES
4
3
0
2
0
H
1
MSM7630
R
0
0
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