msm7630 Oki Semiconductor, msm7630 Datasheet - Page 86

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
5. TMR Operation
5.1 Interval Timer Mode
In interval timer mode counting begins from the value set in the Timer Initial Value Register, and a
timer interrupt is generated to the CPU when the counter overflows.
1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.
2) Set TCMR’s TCS bits to select the counter’s increment clock.
3) Set TCMR’s TMOD bit to "0", setting interval timer mode as the operating mode.
4) To generate periodic interrupts set TCMR’s TCAI bit to "1", which will set the counter to be loaded
5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will
6) Write "1" to TCMR’s TCG bit to start counting. An interrupt will be generated when the counter
7) To release the interrupt set the TSTS (Status Register) TDAT bit to "0" in software.
• bit[4] TCAI
• bit[1:0] TCS
4. TMR Register Addresses
The MSM7630 has two timers. The register addresses for each are listed below.
0 : Disable auto-initialization of timer value register
1 : Enable auto-initialization of timer value register
This bit will be "0" after reset.
00 : Count clock F
01 : Count clock 4 F
10 : Count clock 16 F
11 : Count clock 64 F
These bits will be "00" after reset.
with the value of the Timer Initial Value Register each time the counter overflows. For a one-shot
interrupt set the TCAI bit to "0".
simultaneously write the same value to the Timer Value Register TCR.
overflows.
TMR1
TMR2
Timer Initial Value Register
Timer Value Register
Timer Status Register
Timer Command Register
Timer Initial Value Register
Timer Value Register
Timer Status Register
Timer Command Register
0xF8000000
0xF8000004
0xF8000008
0xF800000C
0xF8000010
0xF8000014
0xF8000018
0xF800001C
MSM7630
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