mt88ebnr Zarlink Semiconductor, mt88ebnr Datasheet - Page 24

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mt88ebnr

Manufacturer Part Number
mt88ebnr
Description
4-wire Calling Number Identification Circuit 2 4-wire Cnic2 Semiconductor Inc
Manufacturer
Zarlink Semiconductor
Datasheet
Notes:
This on-hook case application is included because a CIDCW (off-hook) CPE must be also capable of receiving on-hook data
transmission (with ringing) from the end office.
1) PWDN and FSKen are internal signals decoded from CB0/1/2.
2) The CPE designer may choose to enable the MT88E45B only after the end of ringing to conserve power in a battery operated CPE.
3) The microcontroller in the CPE powers down the MT88E45B after CD has become inactive.
4) The microcontroller times out if CD is not activated.
5) This signal represents the mode of the DR/STD pin.
CD is not activated by ringing.
OSC2
FSKen
TIP/RING
PWDN
CD
DR
Note 5
DCLK
DATA
Note 1
Note 1
Figure 15 - Application Timing for Bellcore On-hook Data Transmission Associated with Ringing,
Demodulated Data
(Internal Signal)
DR (Data Ready)
(Output)
DCLK (Data Clock)
(Schmitt Input)
DATA
(Output)
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
1st Ring
Note 2
A
t
PU
Word N
Word N-1
Figure 14 - 3-Wire FSK Data Interface Timing (Mode 1)
>t
7
7
B
DDS
stop
stop
Ch. seizure
..101010..
>t
Note 1
0
DDH
C
t
start
CP
1
2
Word N
Zarlink Semiconductor Inc.
0
3
MT88E45
Mark
1/f
4
D
DCLK1
1
5
e.g., CID
24
6
2
7
Word N+1
Data
Data
E
t
3
CA
4
F
Note 3 Note 2
stop
5
t
A = 2sec typical
B = 250-500ms
C = 250ms
D = 150ms
E = feature specific
Max C+D+E = 2.9 to 3.7sec
F
PD
2nd Ring
200ms
6
7
Note 2
Note 4
t
RL
stop
Data Sheet
0

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