le58ql061 Zarlink Semiconductor, le58ql061 Datasheet - Page 47

• Manufacturer Part Number: le58ql061
• Description: Quad Low Voltage Subscriber Line Audio-processing Circuit
• Manufacturer: Zarlink Semiconductor

44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
Transmit on A and B
Transmit Edge (Global parameter)
Receive Clock Slot (Global parameter)
Transmit Clock Slot (Global parameter)
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read unless at least one channel is
selected in the Channel Enable Register; however, TAB is channel specific.
* Power Up and Hardware Reset (RST) Value = 00h.
46/47h Write/Read Chip Configuration Register
Interrupt Mode (Global parameter)
Chopper Clock Control (Global parameter)
PCM Signaling Mode (Global parameter)
Clock Source Mode (Global parameter)
The master clock frequency can be selected by CSEL. The master clock frequency selection affects all channels.
Master Clock Frequency (Global parameter)
Command
I/O Data
Command
I/O Data
MPI Command
R/W = 0: Write
R/W = 1: Read
MPI Command
R/W = 0: Write
R/W = 1: Read
TAB = 0*
TAB = 1
XE = 0*
XE = 1
RCS = 0*–7
TCS = 0*–7
INTM = 0
INTM = 1*
CHP = 0*
CHP = 1
SMODE = 0*
SMODE = 1
CMODE = 0
CMODE = 1*
CSEL = 0000
CSEL = 0001
CSEL = 0010
CSEL = 0011
CSEL = 01xx
2 x 1.544 MHz, or 2 x 2.048 MHz)
CSEL = 10xx
4 x 1.544 MHz, or 4 x 2.048 MHz)
Transmit data on highway selected by TPCM (see Commands 40/41h).
Transmit data on both highways A and B
Transmit changes on negative edge of PCLK
Transmit changes on positive edge of PCLK
Receive Clock Slot number
TTL-compatible output
Open drain output
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
No signaling on PCM highway
Signaling on PCM highway
MCLK used as master clock; no E1 multiplexing allowed
PCLK used as master clock; E1 multiplexing allowed if enabled in Command C8/C9h.
1.536 MHz
1.544 MHz
2.048 MHz
Reserved
Two times frequency specified above (2 x 1.536 MHz,
Four times frequency specified above (4 x 1.536 MHz,
Transmit Clock Slot number
INTM
D
0
7
TAB
D
0
7
CHP
D
Zarlink Semiconductor Inc.
1
6
XE
D
1
6
SMODE
D
0
5
47
RCS2
D
0
5
CMODE
D
0
RCS1
4
D
0
4
CSEL3
RCS0
D
0
3
D
0
3
CSEL2
TCS2
D
1
D
2
1
2
CSEL1
TCS1
D
1
D
0
1
1
CSEL0
TCS0
R/W
R/W
D
D
0
0