le58ql061 Zarlink Semiconductor, le58ql061 Datasheet - Page 68

• Manufacturer Part Number: le58ql061
• Description: Quad Low Voltage Subscriber Line Audio-processing Circuit
• Manufacturer: Zarlink Semiconductor

General Structure of Other Commands
When the QLSLAC device has completed transmission of the channel ID information, it sends an EOM (MX = 1 for two
successive frames) on the upstream C/I channel. The QLSLAC device also expects an EOM to be received on the downstream
C/I channel before any further message sequences are received.
When the monitor channel address byte is 81h, 89h, 91h, or 99h, the command byte is interpreted by the QLSLAC device as
either a Transfer Operation (TOP), Status Operation (SOP), or a Coefficient Operation (COP).
Commands are sent to the QLSLAC device to:
n
SUMMARY OF MONITOR CHANNEL COMMANDS (GCI COMMANDS)
Coefficient Operation
Read the status of the system without changing its operation (Transfer Operation (TOP) command)
Write/read the QLSLAC device operating state (Status Operation (SOP) command)
Write/read filter coefficients (Coefficient Operation (COP) command).
Channel Information
Transfer Operation
Status Operation
Commands
Commands
Commands
Commands
Command
Address Byte
A = 0; Channel 1 is the destination
A = 1; Channel 2 is the destination
B = 0; Data destination determined by A
B = 1; Both channels 1 and 2 receive the data
SOP 10
SOP 12
SOP 13
SOP 14
SOP 11
SOP 1
SOP 2
SOP 3
SOP 4
SOP 5
SOP 6
SOP 7
SOP 8
SOP 9
COP 1
COP 2
COP 3
COP 4
COP 5
COP 6
COP 7
COP 8
COP 9
TOP 1
CIC
C#
C8/C9h
6C/6Dh
4A/4Bh
E8/E9h
4D/4Fh
8A/8Bh
9A/9Bh
70/71h
46/47h
60/61h
54/55h
50/51h
80/81h
82/83h
98/99h
86/87h
88/89h
96/97h
Hex
0Eh
00h
73h
00h
02h
04h
53h
D
1
7
Channel Identification Command (CIC); Requires unique address byte (80h, 90h)
Read revision code number
Deactivate channel
Software Reset
Hardware Reset
Activate channel
Write/Read Operating Conditions (Configuration Register 1, CR1)
Write/Read Chip Configuration (Configuration Register 2, CR2)
Write/Read Operating Functions (Configuration Register 3, CR3)
Write/Read SLIC device I/O direction and Status Bits (Configuration Register 4, CR4)
Write/Read Operating Mode (Configuration Register 5, CR5)
Read SLIC device I/O Register
Write/Read Debounce Time Register
Write/Read Ground Key Filter Sampling Interval
Read Real-Time Data Register
Write/Read Interrupt Mask Register
Write/Read AISN & Analog gains
Write/Read GX Filter Coefficients
Write/Read GR Filter Coefficients
Write/Read Z Filter Coefficients (FIR)
Write/Read B1 Filter Coefficients (FIR)
Write/Read X Filter Coefficients
Write/Read R Filter Coefficients
Write/Read B2 Filter Coefficients (IIR)
Write/Read Z Filter (IIR)
Zarlink Semiconductor Inc.
D
0
6
68
D
0
5
D
A
4
Description
D
B
3
D
0
2
D
0
1
D
1
0